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Your second circuit doesn't make a lot of sense to me. First of all, I think you may damage the FSR with such a high voltage. Secondly, what's the point of the cap on the wiper? Thirdly, why do you think you'll damage the pot "when it is at minimum resistance"? It's always a 100K; you've already shown there's less than a milliamp. Look at using a
Hi, Please assist in telling if noise could be coupling into our DCDC module via the ground plane that we have underneath the module? Maybe we should remove the ground plane under the Vicor DCM3623T50M53C2T00 DCDC module? We have connected pri and sec grounds and have that joint ground directly under the module. Maybe this is why Vicor have a
if samples(i) = I(i)+jQ(i) then you method is correct. You calculate the mean rms voltage over a given number of samples and from it the power. You could also calculate before the power "P(i)" of the i-th sample then calculate the average of the vector P(i). The first one should be less sensitive to isolated peaks over the I/Q samples.
Hi~ I read papers, but a problem really make me puzzled. As the picture attached below, the impedance at gate terminal became negative after an inductive impedance connected to the drain of an MOS device. 158391 While, in my mind, I think the impedance at gate is extremely large rather than negative? Does anyone kn
Sounds good except pad #1 is much quieter than all the others. Have to hit it hard to get anything.
Hi Edaboard community, I am trying to simulate a homogeneous CPW structure using HFSS and for exciting the quasi TEM mode of this structure, I am defining wave ports at the ends of the structure. I have computed the Poyiting vector at the surface of the wave ports; and I notice that the value is not always the same and that for certain freque
Hi all. How do you overcome a click back on the diode voltage of a current mirror when you enable it?
Hi, We wish to do Transient testing of our 3720W power supply. No_load to Full_load to No_load?.. Please could you advise if there is a quicker/cheaper way to do this than the attached? We need the three load switchs to switch at the very same instant. The power supply uses Vicor DCDC modules.
Circuit #18 will probably work in a simplified simulation circuit, less likely with real components. Power SCR need a certain amount of trigger current that can't be provided by an analog opto coupler. For the intended phase angle control, you want to generate a trigger pulse with variable timing. Circuit #18 isn't particularly suited for this p
Hello, I saw this layout where the designers extend the NPLUS layer between two PMOS transistors in NWELL technology, the two transistors are not sharing the drain or the source, so how he can merge the NPLUS layer in between ? thanks 158305 - - - Updated - - - Sorry, th
I would not take anyone's opinion besides the foundry's reliability documentation (you want it in writing, yes, you do). Especially since you seem to want a specific life expectancy, only the foundry's guarantee is worth anything. Other than maybe a very well conducted reliability qualification exercise (sound like fun? It ain't, even when
There is four fed patch for circular pol (see Attachments) simulated in CST. When 1 port is excited the S31 is about -4dB, S21=S41=-13dB, S11=-15dB. It means that total efficiency of antenna is less than 60%, because ~40% of power return to the port 3. When all ports simultaneous excitation are performed the efficiency more than 95%. Why (...)
Suppose the power saving of design is D, which is supposedly lower than current benchmark systems. Suppose such design provides a good compromise of speed. memory and power Suppose i added nop instruction(no instruction instruction) into the microprocessor. Since nop now provides an advantage over other systems. by survival of fittest logic, if
I have a question that came up during an experiment. I hooked up a function generator to a coil and to my surprise the voltage across it went from 4.48 volts at 100 kHz to 800mV at 1 mHz then back up to 4.04 volts at 4.9 mHz. I thought as the frequency went up current went down in an inductor. This one went up then down. Am I missing something?
Hello, I have designed a rising edge D-flipflop as shown bellow using CML method. I could have just connect the output to NMOS switch and discharge it to ground. However in our reset signal comes at Q, so basickly if we have Q=1 then this Q=1 is used to turn Q into Q=0. so we have oscilation. How do i add "reset" to my D-flip flop So i could
Just curious if anyone has any recommendations for PCB processes or finish types for the most durable pads. The application is a docking-type cradle where one side of the PCB will be exposed to air, fingers, etc with only pads and mask (no components or solder). I think the standard soldermask and ENIG copper pads are fine, but if there's any
It has been proven a lower noise alternative for my circuit The Jfet ones I have tries yielded in weird oscillations and other problems and also not lower noise (hiss) The op-amp stages have virtually no gain so I doubt there is any real advantage in using super low noise amps. Almost all the hiss will be coming
Obviously, stability is a necessary condition for the design. All other parameters, like more or less "disturbance" in the sensor signal, are meaningless without specifying the exact purpose and intended dynamic behavior of the control circuit. Not sure if you have specified it at all. You may want to "clamp" the instantaneous output current, bu
Hello I design a four-quadrant analog multiplier and plot it's gain and phase bode plot. then I try to determine phase margin and analysis stability, but I figure out that phase margin=110 degrees. I don,t have an idea what does the phase margin=110 degrees mean?:shock: Is it stable?:roll: please help me thanks 158199
Hi ALL, I want to combine two CGHV59350 GaN devices in ADS using 90 Degree Hybrid at 5.6 GHz. The simulation is done for single device and simulated results are as expected. 90 Degree hybrid also works fine. The problem arises when I use this hybrid for combining . The output is 2.5 dB less them expected .has anyone done simulation for c