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max loop bandwidth should also be well less than the RHPZ fequency, (assuming you are in CCM).
Most easily achieved by omitting useless R6. Otherwise must connect a dummy resistor from RG node to ground, e.g. Gohm value.
THe Triac is rated for 600Vp and the motor locked rotor current is (5.02 Amps rms) So the voltage of the MOV must be less than 600V at the rated locked rotor current when the triac is open circuit. The QUestion is, what is the inductive energy stored in a "locked rotor" or motor changing direction at zero speed, when switched off that must (...)
I want a circuit that inputs V volts and outputs V-Vth volts, where Vth is the threshold voltage of a pMOS or nMOS. Is a circuit possible? I tried with pass-transistors, its not happening.
When secondary current falls to zero, there may still be some residual magnetic energy stored in the core which leads to a ringing waveform in the primary. This is a result of having less than 100% perfect coupling between primary and secondary. The looser the coupling, the more likely the voltage waveforms in primary and secondary will (...)
Because of the high value of R1, the incoming "voltage" is actually more like a constant current , the output will be more or less a square wave -.8V -> +5.8V P-P. The problem is that at the peak of a sine wave, nothing much happens, it goes from 99% -> 100% - 99% of the peak voltage. I would use a single hi gain NPN transistor, use a 10K collec
I got this warning when back annotating an sdf file. What exactly does it mean and will it cause any problems? ncelab: *W,SDFNL2 (,35120|7): The sum of the two annotated limits to $setuphold, $recovery or $recrem timing checks are less than zero for instance :UUTreg , setting negative limit(s) to 0 <...sdf, line 17994>.
This is nothing but just a clock divider code. If the input clock is 50MHz, then the output will be 1Hz, means its a divide by 50,000,000. But there are mistakes here 1. If you really want 1Hz, then you should give 24999999, instead of 25000000, because the counter includes the zero, or you can put the less than (< ) operator instead of (...)
Hi all, Im working on BLDC sensorless algorithm using zero cross detection but i have a weird problem, the back emf appears when duty cycle is 100% is 95966 and with duty cycle less than 100 is 95967 while ideally when phase goes from low to high or vice versa, its in slope form, but it is not th
Each logic family specifies its input requirements to recognize a logic one or zero as VIL and VIH. For example for TTL ViH =0.8v and VIH=2.0v. Any value less than .8v is considered a logic zero and Any value greater than 2.0v is considered a logic one. An input between .8v and 2.4v is invalid. Similarly the (...)
Maybe subtract your desired number (which is 6), then do: BEQ (branch if equal to zero) BNE (if not equal) BMI (if minus) BLT (if less than) BGT (if greater than) The 'branch' command jumps forward or backward the stated number of bytes (in two's complement).
If X is an 8-bit value it can't be more than 255 and a check for less than zero is meaningless if it's an unsigned value so I'm guessing it's an 'int' (signed). It isn't a function in the programming sense, it's a query. It reads as "if the value of X is more than 255 or the value of X is (...)
I think, R4 is intended to achieve safe behavior in case of wire break. I don't exactly understand what you intended by omitting it? The shown TC amplifier is less-than-perfect, because TC respectively wire resistance have a certain effect on zero and scale. It might be a problem either with long wires or very thin TCs that can have up to (...)
How do I know if the accelerometer is 0 degree or 180 degree when they have same output value?You'll get more ambiguities by rotating the accelerometer around other axes. For an unequivocal detection of spatial orientation, you need not less than 3 orthogonal accelerometer channels.
Hi, I have an all-digital design that would benefit greatly from the ability to add fine-grained, in-the-field adjustable delays significantly less than one gate delay (FO4). These delays are not critical to functionality -- if they don't work, the chip won't be a total loss; it will simply underperform. My plan is to include current-starved in
There's a manufacturability gap where you can't reliably pattern below a certain spacing. zero gets merged, any as-printed spacing less than your well depth has a chance of the implant drive connecting them anyway. Then there's the question of just what a narrow-base lateral NPN looks like, to your circuit.
You are best to not exceed the motor current rating as well.. Can you drive with zero Volt by shorting Motor with no Voltage applied then remove short then apply reverse voltage in rapid sequence? The FETs ON resistance ~5 mOhm, if much less than ESR of the motor then most of the energy will be dissipated in the motor., but that may still (...)
The easiest way is to level-shift the pulse train up into the positive region. Attenuate as necessary so it ranges from zero to 5V (or your supply V). Incoming positive pulses will become higher than V/2. Incoming negative pulses will become less than V/2. Idle periods will be at about V/2. You must set thresholds for (...)
hi guys, I am doing a fuzzy based mppt controller for PV array. now from different sources i have seen that the output membership function which is duty cycle is in a range of -4 to +4, now my question is that if we need a value of less than zero as duty cycle to get mppt, then how to use that negative voltage as duty cycle because duty (...)
SSRs often use Triacs or SCRs, not just MOSFETS. You MIGHT be able to design a less expensive discrete solution, but other nice features like zero-crossing, etc. will add complexity. You need to consider the tradeoffs.