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Hi all~ I'm trying to simulate the phase noise of my VCO and I used EM simulator to extract port to port s-parameters (all ports including IND and MOS,,...) and applied the results to cadence schematics through nport in analogLib. PSS/Pnoise results of phase noise in cadence was so bad and it shows difference of more than 10dBc/Hz compared t
BW=29 MHz NF=3.1 MDS=-174+3.1+10*log(BW)=-96.xx dBm.. Bandwidth and NF is pretty high to measure -100dBm signal strength.( I didn't include necessary S/N !!, it should be around more or less 10-12dB for safety ) It will somehow work but the sensitivity may not be as you desired..
I need to work on a project where the microcontroller should: 1-)Read three voltage outputs of an accelerometer 2-)Log the data to an SD card 3-)Send the logged data to cloud by intervals via a GPRS module The requirements are to make it cheap and most importantly low power. I will have enough time for this I guess. But since there are zil
Dear friends, I am trying to design a floded cascode OTA for the sample and hold circuit that should work with sampling frequency of 5 MHz, this requires me to have an OTA with a typical GBW of 100 MHz. I am using 0.35 um CMOS technology with channel length I st for all the transistors to 1 um. The problem I am finding it very difficuilt to a
Hello to all ! getting some info from AN1292 (Texas application for LM5642 ),I made dc-dc converter to use at a solar controller. At test with no load the converter not work . no output, no pulses 200khz to drive mosfets. it seems to be disable ( on/ss pins below 2volts ). I was checked hardware for errors many times , but I don't find something
Hi, I'm using Lenovo, when I try to install Linux my laptop got stuck after I switched it off and on. it's not working, all lights up but the screen is blank, CPU fan is running 3 sec only, can anyone help me with this, please.
156744 Hi, For a typical double balanced Gilbert cell, how to match the RF input to 100 ohm? The zero frequency input impedance should be infinity. Even when frequency increases, the input impedance doesn't change significantly at sub-6GHz range. I understand that inductive degeneration can help with input-match
I would size this LDO pass element depending on desired Vout, say 5V, drop out voltage, say 1V, so i need at least 6 V in the current requirement has to be the maximum current the load will draw. plus a little margin what is the actual input voltage? your device is drawing, ??? per digital circuit at its highest frequency? (let's say 5 mA fo
First of all yes it is homework but I worked on it and stuck at only this part. Maybe I am approaching on wrong side I am open to every advice. I need to design a environmental noise checker circuit. I am not allowed to use any IC except OPAMPS! Passive elements (resistors, capacitors, inductors, diodes), LEDs, Analog Microphone, DC Power Supply
thanks sir for your reply, what do you mean by other PCB package ? do you mean other software like eagle,kicad...etc ? also is it possible to make the layout manually by putting transmission line between each lumped component or it's useless ?
In ASIC design, is there any relation between IR drop and Noise Margin ? and If yes, then how?
I agree with FvM. For these small attenuation values, there is a lot of variation in shunt resistance required, to keep the 50 Ohm input/output impedance. Hm... that makes me think. How about this one? It uses a stereo potentiometer of 50R. The tracks are part of the input and output Pi attenuators and thei
Hi All, am appealing to anybody who has a similar environment to give me a few tips here :) The internet problem is weird, the system default is ffox 70 that runs fine standalone but none of the quartus menu's that would invoke it (help etc) work you just get no response. The same is true even if you set the browser path directly to ffox instead
hi in this schematic i want to use uc3846 instead of sg3525 and control the primary i need to add a sense resistor (and rc filter)and use suitable caps and resistors which are in datasheet to run uc3846. but is that needed to change other schematic parts?like add or remove other components? 156723
Suppose the power saving of design is D, which is supposedly lower than current benchmark systems. Suppose such design provides a good compromise of speed. memory and power Suppose i added nop instruction(no instruction instruction) into the microprocessor. Since nop now provides an advantage over other systems. by survival of fittest logic, if
Therefore it's a reactive load. It may cause AC voltage crossings to be out of alignment with AC current crossings. Then you're not certain which you are sensing. Or it may cause continued current flow through the triac, causing it to stay On after it's supposed to turn off. - - - Updated - - -[
A typical BPF should has 1dB ( more or less ) Insertion Loss at those frequencies, not 10dB. This Insertion Loss will surely reduce the Sensitivity of the Receiver but it's obligatory.. If the Antenna Impedance varies so, I believe this antenna is not very well designed.Nevertheless, Signal Levels are pretty high at FM Band.So, I don't think that t
Hi everyone, In our lab, we are going to design with 65nm technology. I'm responsible of a team who's in charge of microelectronics integration. We'll have to bond on pad in 65nm technology and I have no idea for the pads size. We allready "wedge bonded" many and many chips with pad size around 100x80um but with 65nm I wonder what are the constr
Can you please tell me any three important differences between Artix 7 xc7a35tcpg236-1 vs Stratix III EP3SL150F1152C2 FPGA. It is going to be helpful for my exam.
Hello there, I'm curious why the PN junction of a BJT transistor is still used as the CTAT voltage in a reference circuit (bandgap), while a MOSFET threshold voltage also has CTAT behavior? Is it because the BJT has exponential behavior while the MOSFET is just the square of the voltage? Why is the BJT better? thanks