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# Linear Region

236 Threads found on edaboard.com: Linear Region

## [Moved]: what can I learn from this positive voltage pump design?

1-Those are semiconductor capacitors but I don't know what type they are.. 2-The MOS are not diode connected, they have been used instead of resistors ( may be voltage controlled, depends on Vint ) or they are simply Pull-Up resistors.Vgs=Vds so the MOS operates in linear region being as resistor

## MOSFET resonant switch

You'd still need a driver to excite the RC tank and once you have a driver it's best to use it to drive the actual gate directly. Assuming the mosfet is switching power, you want a strong driver to limit time in the linear region. Though there are plenty of applications that use basic oscillator circuits in power applications, there is few bene

## How do you find gain of a CS stage (say) if MOSFET is in linear region?

Is the small signal model still valid?

## power amplifier bias voltage_ making power amplifier in the saturation region

I am told that power amplifier should be biased at saturation region. For the bipolar process, as shown in the figure, the saturation region( linear region) is at the left side, which is different from the saturation region of CMOS. 133664 So I need to bias the power amplifier to the B node, right? (...)

## Help!! Questions on All types of resistances in Transistor model.

These differences pertain to mode of operation mostly. "On" resistance is resistance, desired to be low, from drain to source in the hard-gate-driven linear region. Of course a weakly driven FET has an on resistance too. Just lousy. "Output" resistance -is- "on" resistance, when the FET is "on". But it's more of interest (i.e. different interest)

## this strongarm D flip-flop

133280 1)#1, which is an alway turned on transistor and that acts as a resistor? it's Not degeneration resistor. what is that for. If it's acting like a resistor then it much operating at linear region. 2)#2 why there's a cross coupled nand gates? 3)#3 Is that a cross coupled element used for as latch, for stoarge?

## Offset votlage using transient

Yes, you can. Yes, people do. But there are a couple of things to watch out for. One is, the ramp time through the linear window of the front end (that is, in the second chart from ata_sa16, the region where the ouputs show any non-flat-line quality, plus some) must be much less than the delay time through the amplifier or you will pick up an er

## Facing Prblem with Noise figure of Cascaded System

Cascading NF specification of a system is valid only and only if the system is linear.( or the since the system is in linear region)Otherwise, non-linearity will bring more or less additional noise and this relation will not be valid anymore as in your system that includes a high nonlinear element frequency (...)

## [Moved]: VIH, VIL, VOH and VOL in a demux, mux, decoders, etc

For a triangle waveform to produce the same result as a DC hysteresis sweep, the delay of the path in question must be << the ramp time -through the region of interest- (e.g. the linear window of an inverter chain). A 1uS total rise time and a 10nS prop delay will give you 1%-ish error if the whole range is linear, 10%-ish if only (say) (...)

## [Moved]: why a PMOS gate connected to ground permanently is a linear region device?

So, do you agree that the PMOS connected its gate to ground is a linear device? do you agree that the PMOS connected its gate to CLK is a saturation device? No. PMOS w/ G=gnd! is linear provided that the drain is at some point above gnd!. At D=gnd! it is possibly still in saturation as |Vgs-VT| < |Vds|. Without def

## OTA error amplifier in LDO

I had some questions in LDO design when it comes to the error amplifier (EA) 1) Why is it advantageous to use OTAs when designing the error amplifier in LDOs? I know that we utilize OTA when we are driving small capacitive loads and voltage amplifiers when driving high impedance loads. Since the output of the EA is connected to the gate of the

## Multi-Channel system problem

A sequence $x$ is the output of a linear time-invariant system whose input is $s$. This system is described by the difference equation $(1.1)$ $$x=s-e^{-8\alpha}s$$ $$\alpha>0$$ a) Find the system function $$H(z)=X(z)/S(z)$$ and plot its poles and zeros in the z-plane. Indicate the region of convergenc

## [Moved]: what is linear and slew limited stages in comparator

126451 The region where the Vout is some constant times the Vin is called the linear region and where the output saturates due to slew limits or the maximum deliverable output current limit is called the slew rate limited region.

## [moved] influence of LAMBDA, current and Vds on rds of MOSFET in saturation regio

... how can i expect rds for a specific vds , how LAMBDA influences for currents (becauseit varying very drastically with high curretns? Find here an Id vs. vds plot of a MOSFET: 125969 Here you can see rds vs. vds: in the linear region rds is essentially constant for

## RF Power Amplifier Frequency Limitation

s-parameter is small small signal but provided you are operating in linear region, it should give you good estimate. since you have nothing other then s-parameter, its good to simulate it cos you have no other options available!

## How do you design a voltage controlled variable resistor for low voltages?

I still want to get a linear change in resistance even below the cutoff/threshold voltage (0.6-0.7 V), is there any mechanism or other circuitry which can be used to achieve this ? The resistive part of the Ids vs. Vds characteristic (called triode or linear region) has nothing to do with the MOS

## translinear principle of mosfet

Hi i know translinear principle is nothing but the relation of transconductance and the collector current and also MOSFET in the sub threshold region have a linear behaviour. So my doubt i am not able to find if a topology of transistors build is in the translinear closed loop. Will transistor only in closed loop form the (...)

## 4N25 model in LTSpice, CTR too high?

The minimum CTR is the only parameter which we should consider for use in applications working saturated. Considering that manufacturers specify CTR within a wide range, a simulation would not give a reliable result for a linear region.

## Operating regions of a transistor switch

If operating as a switch, you go from saturation to cutoff (or other way round) as you mentioned. As Vbe increases, for a short amount of time, the transistor will be in active (linear) mode until you enter saturation. But you want to design such that it spends as little time as possible in the linear region.

## thermometer with pt100 and atmega8

The resistance variation for 1°C increase in temperature is about 390 mΩ. for I mA current and accuracy about 0.1 °C the voltage will be 39 ?V You need to calculate the bias current so that the curve fit within the less non-linear region of the sensor. Keep in mind that PT100 sensors are not totally linear