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Lna And Linearity

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42 Threads found on edaboard.com: Lna And Linearity
Hello All, I was on phone interview for RF designer, and was asked, "Tell me how does the lna make it all happen in low noise?" In fact, I never thought that before (though, I did a class project on lna design in Cadence). I replied from my gut feeling: 1. It does not have resistors that add thermal noise. 2. There are inductors in the
I want to design a cmos lna circuit in AWR. I built in AWr and run.But I can't obtain reasonable result. I think I can't choose the right element.Could someone give me an example circuit,Please?
Hello all, I have few questions related to linearity of lna: a) How does the 1 dB compression point and IIP3 point changes with the number of fingers in the transistor? I am using 400um transistor. Without adding any number of fingers, P1dB is -22dBm and IIP3 -14.6dBm. But when I changed it to , 14 fingers with (...)
linearity parameters are rarely measured on a low-noise amplifier with a gain below 20 dB. You never indicated what signal level your lna should handle. In a good receiver, stages AFTER the lna are important in linearity considerations. With your lna, you should indicate the typical signal (...)
I am going to design an lna for 60ghz or higher . I have read some texts and papers but I couldn't gain a good viewpoint about of which type of inductor ( transmission lines , active inductor , pasive spiral inductor ) I have to use in my design with respect to all things such as area , power , linearity . noise , gain , stability (...)
Hey Guys, I have been designing a Low Noise Amplifier from 1 to 3 GHz. I am searching for a transistor for my work. Earlier I had used ATF54143 for the design. My goal is to achieve 30K of noise temp throughout the band and its P1dB should be +20dBm atleast. ATF54143 works fine till 2 GHz (~30K from 1 to 2 GHz). The noise temp in a two stage (...)
S12 lna isolation The S12 isolation measurement between the output and input of the lna has no relationship with measuring the lna's linearity (IP3), 1db compression (P1db) or point and lna BW correct? ---------- Post added at 01:50 ---------- Previous post was at (...)
hello all.. For CMOS Ultra Wideband applications (UWB) of Low Noise Amplifier there exist a trade off between few design parameters viz.... 1. power consumption 2. wide bandwidth 3. Moderate but flat gain on entire BW 4. Low Noise Figure 5. linearity / IIP3 i m searching of IEEE papers but every i found so much confusing trade (...)
Dear all, I work for a RF receiver system design now. I need define RF down-conversion mixer parameter and circuit that mixer following lna. One of RF mixer circuit performance is Gain=3dB ,IIP3=9dBm OIP3=12dBm; another circuits RF mixer performance is Gain=10dB ,IIP3=2dBm OIP3=12dBm.From reduce the receiver NF, i could choose the second RF down
Yes, generally a Line Amplifier is a linear wideband amplifier, when generally PA's and lna's are narrowband.
If you use pHEMT in cascode configuration, you may obtain wideband lna with relatively low noise and high gain. Look at for discrete pHEMTs..
Hi,everyone I am now to design a 1.5G lna with two gain mode in cmos 0.18 . The architecture is attached later.When Vg1 is 1.8V, and Vg2 is 0,lna is high gain mode;but,when Vg1 is 0 and Vg2 is 0.6V,lna is low gain mode.The post simulation shows a bad linearity in low gain mode,that is (...)
Hi, I am designing wide band lna and freq range is 0.7~2.7GHz am using noise cancelling technique, but gain is not flat. and linearity is poor in 0.7GHz than 2.7GHz. Is there possible to use shunt peaking inductor to get flat gain and how to improve linearity (I'm (...)
Hi, I am designing wide band lna and freq range is 0.7~2.7GHz am using noise cancelling technique, but gain is not flat. and linearity is poor in 0.7GHz than 2.7GHz. Is there possible to use shunt peaking inductor to get flat gain and how to improve linearity (I'm (...)
Dear all I am rookie in MMIC field. I am very puzzled by matching of 3 stages lna the first stage is matched for minimum noise figure, this is easy to understand. but how about the second and third stages? I know the last stage is of concern about linearity but how we do to get better linearity. (...)
I am working with an lna with CMOS transistors and read that an inverter have better linearity than a CS-stage but it didn't say why? Anyone know why or have a good reference to suggest?
dear oabedi the firs chapter of "Silicon-Based RF Front-Ends for Ultra Wideband Radios" compares some lna architectures. you can get it from gigapedia. have fun. vahid
I cannot do anything about sheiding beacuse its chip but i can vary the power supply of different stage in IC by programing like supply to IF filter lna and LO so which can effect most to reduce these spurs. I am measuring at I Q before ADC and yes when input is low spurs didnt seems to appear
Hi, I'm designing very high power amplifier for wireless communications (2 kW), in my case efficiency/linearity is the bottleneck. For satellite communications I think that the bottleneck is lna, but also good efficiency is important, and good response to extreme enviromental factors such as low/high temperatures, inmunity to cosmic (...)
Dear All, I'm designing a WCDMA mixer for ZIF Rx and i'm using the Micromixer topology as my lna is single ended.. I am simulating the linearity by using the QPAC and QPSS method and i made a parameteric sweep on LO amplitude (btw, it took a 1h 48 mins on 8 processor machine :)) .. the problem is that (...)