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18 Threads found on Load Stability Circuit
Before designing the feedback amplifier, you would make a specification. load impedance range, amplifier DC and AC characteristic (either gain versus frequency or characterized in time domain), intended accuracy. Presently you have a relative low, frequency independent loop gain (P controller). The gain won't suffice to cancel DC errors but can
Hello, Attached is a picture of an opamp with capacitive feedback. I think the load seen by the opamp is = Cf + C1 + diode ON resistance. Is this correct ? How do I determine the stability of this circuit in Cadence or any spice simulator ? Thanks.
You're right: this cascode circuit is not very temperature (nor supply voltage) stable. But at least Q1's Vc will stay 1*Vbe below Q2's Vb. The Figure 2.24 text just says the current stability referred to load changes is improved (compared to a simple constant current source). This is true, because the cascode transistor Q2 (in base mod
I have biased my circuit and i have check the stability. Now my next step is i want to match the 50 Ohm impedance to load impedance here in my case load is Transistor. So i have used the following methodology for my impedance i.e., first i have loaded the s parameters of a transistor then i have given the (...)
At very light loads / no load, you may not get enough o/p out of your aux winding to power the IC properly and it may be re-starting. Also the gain of the power circuit is different at no load and a slight amount of PWM will cause the o/p to go overvolts, stopping the PWM (and the aux output) until the Vo drifts back to (...)
89975 In the attached circuit is driving capacitance load and current of 5mA. sense and vdd_1v8 pins are shorted outside. To check stability and see loop gain and phase response for this circuit, where exactly i need to break loop?
Hi, I have been working on this project .... Let me describe the circuit so far... This is kind of load transient tester by linear... I am developing the similar electric load...but with capability of higher slew rate and high current at low voltage... at least 5, at 0.5 and current of 22 at the same condition... I have been ab
large bandwidth gives you a fast dynamic response that can gives you more tolerance for dynamic changes but the stability could become an issue. small bandwidth is usually more stable but due to the slow response the circuit may not be able to respond quickly to changes in the load current so you will get larger spikes in voltage due to (...)
Your posts are raising two questions: - conditions to achieve stability with capacitive load - required OP parameters for 100 mV AC @ 20 kHz I'll start with the second point. I can't follow your slew rate calculation, but you can easily calculate the required output current. I calculate about 0.25 A for 100 mV and 20 kHz, so it's obvious that
I would be concerned about stability and response to load variation, the LM324 output is weak and the FET gate capacitance can be very large. The gate drive network might want some thought there.
Dear all, I am working on a design of a voltage regulator which involves using a diffpair in a closed loop. However- at low load current the phase margin sucks and the gain is in negative, but to my surprise, it still works in transient analysis. How can this be possible? whats going on? Any suggestions?
Hi, What about your load current, and output cap.. LEE
Zo(s) allone doesn't determine stability, you have to consider the connected load impedance. You can analyze the total output node impedance (parallel circuit of LDO and load) to check stabilty, but the stability criterion would be different to my opinion.
If it is unstable, it means that it will be unstable from the smallest change (noise) in the circuit. As well from the input side or the load side. Only in theory, a ball can stay on the top of a mountain. The smallest breath of wind will cause tha ball to roll down. The only solution is to design the system with enough stability (...)
Because I can't use spectre,I need to simulate the stability of sc_cmfb circuit using hspice. I break the cmfb point and add the equivalent load at the output of the cmfb, then using the dc point with cmfb to doing ac analysis to see the phase margin.I'm not sure whether the method is right. Can anyone give me some suggestion? Thank you (...)
Due to the switching behavior Class E are rather power converters than amplifiers, when the output voltage is entirely determined by the supply voltage and load network elements. In this case the stability shouldn?t be a problem but you have to look for the stability of the entire circuit, when usually the Class E final (...)
IN a closed loop, A common-source with resister load followed by a two stage basic differential op amp. Each of them has a low freqence poly ,How to split them. Use nested Miller compensater or others ? Thanks
Hi, 1) First, what is the intent of your main circuit? You have the input at gate of NMOS differential pair tied to gate of an NMOS load (positive feedback?) 2) You have shorted the output with a resistor (Why?). 3) For stability analysis, you have to keep Rc in place - the second picture shows that one of the Rc is missing. 4) (...)