Search Engine

Load Stability

Add Question

126 Threads found on Load Stability
If 0stability is desired one but conditional stability may be accepted in such cases.Unconditional stability must be valid up to Fmax of the transistor so no combination of load and/or source load will drift the LNA into oscillation regime. (...)
Before designing the feedback amplifier, you would make a specification. load impedance range, amplifier DC and AC characteristic (either gain versus frequency or characterized in time domain), intended accuracy. Presently you have a relative low, frequency independent loop gain (P controller). The gain won't suffice to cancel DC errors but can
Seems modeling problem if the datasheet says that the transistor is unconditional stable whatever the load is.
Do you mean that you want Vout=2*Vin? Or that you want an {error amp to output} gain that ensures stability given the op amp frequency response, output filter and feedback network details? You want high enough loop gain that load regulation is decent and PSRR is driven down to amplifier-internal limits, but not so high that you haven't gone t
Is the voltage ripple acceptable or causing any problems ? I suspect it is due to excessive phase shift in the LC filter with high Q resonance affecting the loop stability. What happens when you shunt the choke with a 5 Ohms? What happens if you apply a 1 A pulse load with 100mA steady load? Is it stable? Does it ring at the same (...)
Hello, Attached is a picture of an opamp with capacitive feedback. I think the load seen by the opamp is = Cf + C1 + diode ON resistance. Is this correct ? How do I determine the stability of this circuit in Cadence or any spice simulator ? Thanks.
I suggest you start injecting signals into an active load and monitor V,I for gain phase stability. You can get a sweep generator from Audacity, and use the audio inputs AC coupled as required to measure the response in time and frequency spectrum, or use scope for unity gain and measure phase margin, 130795
If I had to pick one or the other, I'd go with a harsh load step over the AP300 because you get to see both small and large signal response, and I've seen more "WTF?" involving the latter. Nothing against the AP300 or the need to diligently stabilize the design, just that small signal stability is not the end of it and a simple test method lets yo
Hello, We are using a PRM48BH480x250A00 power module (48Vin to 48Vout) to give a 1.5V, 95A output by using a VTM48EF015T115A00 ?electronic transformer? (NP/NS = 1/32) downstream of it. The actual load on the 1V5 rail is about 600 ASICs. Page 31 of the PRM48BH480x250A00 power module datasheet states that there are definite limits on the
i doubt it woudl be stabe with any output cap between 0 and many mega farads over the entire load range. Here is sim to look at to experiment a bit. (ltspice) You just need the transfer function of the power stage, error amplifier and modulator.....times them together, and get the gain and phase margin.
It doesn't appear to be based upon sound design principles, rather sort of trail and error approach. I suspect the output will be oscillatory under transient load testing. Maybe the user can enlighten us with a description of how it is supposed to work?
here is sim in free ltspice of linear around with compensation r and c and see its stability/response change. Do load stepping to see if you can get it to go unstable aswell. You kind of get the kind of value ranges of the compensation r and c which bring about a nice slow stable feedback loop....then you can check it with a gai
The stability of any feedback system for voltage and current is challenging from no load to full load or dynamic non-linear loads, lab supplies with these features tend to be more complex. This is similar to the feedback gain going from 0 to
If this is your 1st SMPS design, you might consider an inexpensive PC PSU. Historically older designs required 10% minimum load for stability. There are at least a dozen requirements to consider before you start a design.
CMFB effects on stability will result (1) from additional output load by CMFB inputs (probably negligible), and (2) CMFB output impedance change of control element input impedance, s. p. 18 of
hi, I'm desiging a power supply and there is what I have for start problem is that the current limit shors the adj to ground and that makes the regulator go down to 1.2V instand of 0V. I cant use a constant voltage negative supply instand of ground because this voltage a
A simple differential one-stage amp with constant current source and diode connection load should do. No stability problem.
There will be 2 speed control loops and 2 field control loops with a reference voltage for each to match the outputs with no load. When combining 2 voltage sources with and without a load, there be stability problems to resolve with no load and mismatched source impedance ; winding , cable resistance and field regulation (...)
You're right: this cascode circuit is not very temperature (nor supply voltage) stable. But at least Q1's Vc will stay 1*Vbe below Q2's Vb. The Figure 2.24 text just says the current stability referred to load changes is improved (compared to a simple constant current source). This is true, because the cascode transistor Q2 (in base mod
I have biased my circuit and i have check the stability. Now my next step is i want to match the 50 Ohm impedance to load impedance here in my case load is Transistor. So i have used the following methodology for my impedance i.e., first i have loaded the s parameters of a transistor then i have given the gain of a (...)