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44 Threads found on edaboard.com: Log Analysis
Could you please help me out in figuring out whether the Pss/Pnoise results are proper or not?Show me analysis statement of PSS and Pnoise. And show me Simulation log file. Is it possible to get different frequencies (an error of 3% to 4%) in transient simulation and pss?It could be, u

log-normal or other non-gaussian / non-uniform stats will have means that are not centered in the span. Nonlinear circuit elements can make response of uniform stats, one-end-weighted. I have not seen the form of stats posted by erikl but the std= appears to make an unequally-weighted distribution?
since the phase detector is running on some very low frequency, and the divider chain makes the oscillator track any tiny phase jump at the detector but making it N times bigger at the VCO output, yes the phase noise floor of the digital detector gets multiplied by 20 log N
there are so many ways to calculate phase noise just by giving the waveform its difficult to tell, if you have power analysis it can be calculated by Phase_Noise = 10*log (Pn / Ps) Pn = Noise Power in 1Hz Bandwidth at particular frequency offset (fn) in Watts Ps = Carrier signal power in Watts or for SSB 108293
Hi, i have designed a LNA using cadence 0.13um cmos technology with bandwidth of 4-6 GHz. My dc and sp simulation run well but my pss simulation keep terminating and show me there is an error. Can anyone please help? I have attached the related images104761104762104763 here.
Just run your MC analysis; after its completion the simulation log output will tell you where you can find the results. This depends on your Hspice set-up.
When I use the Cadence spectre to run the "hb" simulation for 1dB-compression point of a receiver front-end, an error is encounted. The simulation--output log gives the error information as follows: Fatal error found by spectre at time=201.784ns during periodic steady state analysis, during Harmonic Balance analysis 'sweep-000_hb' , during (...)
Dear all, Hi. The question is "How can I calculate network parameters in LTSpice so that the results will be readable from the output .log or .saw (ascii type) files?" In HSPICE, it is very easy to extract network parameters and save the results in a plain text ascii type file. But, in LTSpice the work is not so simple. I was going to ext
Tetramax does not create any log file for the controllability and observability analysis. So using tetramax we can not do that. pl correct me if I am wrong Thanks & Regards
Hi I have some questions about transient analysis in hfss 13. First what does minimum radiating distance mean in PML setup wizard? Why it is fixed on 100 mm. Also why frequencies extracted do fixed at 901 and I appreciate if we can change it? And what does the plot of residual on a log scale mean?
Hi All, I'm using Cadence's Incisive tool to perfom simulation and code-coverage analysis. My desgin has 2 process FSM modelling style (means combinational and sequential logic defined in two separate process). Problem is not able to do FSM extraction getting below message from log file : Extracting FSMs for coverage: (...)
I am looking for views on the LabJack U3 module - U3 | LabJack Am considering it for analog signal capture. Basically what I want to do is: - View the signal on some software - log to a file for further analysis - Interface to it with my own software (to model my algorithms) Views appreciated. Thanks
does anyone can explain how to make a LPDA antenna in MMANA? or does anyone have a file LPDA in MMANA software for my reference... please share it.. MMANA is not a design program, but an analysis program. As such, you can't use it to design a log-periodic antenna. You will have to find a method from elsewhere, and
Well, it is very general question. It depends on type of timing violation. Please provide the log where the violation log can be seen.
1. You should get this info from the MC sim. Output log 2. If you have a single model file, copy it to a new model name and change the parameters accordingly. Then simulate this new model. If you get process & mismatch information from a central .scs model file with several corner sections (typ, min, max, ss, fs, sf, ff) (or separ
Hello, I beginner in cadence, help me please. (sorry for my English) When doing the s-parameters simulation I get such log: ****************************************************** S-Parameter analysis `sp': freq = (100 MHz -> 1.2 GHz) ****************************************************** Error found by spectre during SP analysis (...)
When I tried to find input impedance function's pole zero of a parallel LC network using Multisim pole zero analysis, I get following message " ........... | | doAnalyses: matrix is singular | | | | | | pz simulation(s) aborted " The circuit as well as log file attached. How to correctly perform pole zero analys
You are doing preCTS analysis and Clock tree synthesis, rt?? Clock tree analysis the min/max path where you r seeing?? As far i know it reports in Clock report nd log also for each clock in your design. The min/max path for the CTS is the min/max path clock is reaching to register. ie the shortest and longest path of the clock . For building (...)
does printed LPDA have the same formula with wire LPDA? i have already read the ARRL book about LPDA, but it tells about wire LPDA. What about printed/planar LPDA? Need your help master..
Here are my analysis Lets assume the loss from port 1 to port 2 is 1.72db . Since its a loss , I take it as -1.72db . Using (db)=20 log V2/V1 we get V2/V1 =0.82 or V2=0.82V1 Now , this implies for a 2 way unequal power divider , V3= (1-0.82) V1 i.