252 Threads found on edaboard.com: Lookup
You can have look at the basic working theory @ Its implemented for LPC2148 but the underlying working is the same. You need to generate or use a hardcoded sine lookup table which feeds values to your PWM block and at the PWM output use a filter which acts a D
Microcontrollers :: 04-06-2017 12:19 :: Power_user_EX :: Replies: 9 :: Views: 2339
you need to find an op amp that can run off of at least +/- 30 volt supply rails, and that has a gain of at least 10 at 25 MHz. Digikey will have a lookup search function to find such a thing.
RF, Microwave, Antennas and Optics :: 06-27-2016 09:49 :: biff44 :: Replies: 5 :: Views: 548
Both the BTFSC and BTFSS instructions are supposed from the midrange Microchip's PIC familly.
Anyway, when it is said "many lines of code" don't necessarily means as being not a fast implementation.
You could think about put all the 4 possible results in a lookup table by using the RETLW instruction.
Microcontrollers :: 06-17-2016 12:19 :: andre_teprom :: Replies: 4 :: Views: 655
I'm not aware of a simple single chip DDS solution that includes arbitrary waveforms (RAM lookup table). For the intended low frequency range, a DDS generator with RAM lookup table can be well implemented in a single chip processor. ARM or dsPIC with built-in DAC could be used, otherwise an external DAC.
As your waveforms also include square wa
ASIC Design Methodologies and Tools (Digital) :: 03-15-2016 07:38 :: FvM :: Replies: 7 :: Views: 1292
i work in assembly language with pic16f887
i want to use ROM as readable memory.
like i have used with DPTR in 8051.
what are DB and DT in PIC16?
how can i use ROM with DB or DT direactive for making long lookup table?
Microcontrollers :: 03-01-2016 06:05 :: Noman Yousaf :: Replies: 3 :: Views: 551
In the past, I've implemented a 8b/10b encoder based on a ROM lookup table and it works fine.
But what is the mathematical function behind it?
8b/10b is based on 5b/6b + 3b/4b.
What is the mathematical function that encodes 5b to 6b ?
What is the mathematical function that encodes 3b to 4b ?
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-27-2016 13:18 :: shaiko :: Replies: 2 :: Views: 683
Hello,there could anyone help me to create a PWM signal with variable duty cycle using potentiometer and using a lookup table from internal EEPROM?
I am able to adjust the duty cyle using a potentiometer on RA0 but still have a problem on reading from EEPROM and pass those values to the PWM module,please help.!!
I am using ASM for better prec
Microcontrollers :: 12-22-2015 08:44 :: jean12 :: Replies: 64 :: Views: 4307
Normally it would be a VCO offset by the fmax performed by a voltage controlled cavity resonator using lookup table corrected values for linearity.
1) A large number of smart calibrated digital / voltage controlled filters are required. (DVCF) as follows;
a) intermodulation tracking notch filter
b) tracking bandpass filter
RF, Microwave, Antennas and Optics :: 10-27-2015 04:27 :: SunnySkyguy :: Replies: 3 :: Views: 503
I'm trying to do Sdevice simulation of InAs Tunnel FET given by Penn State Univesity. im getting Id value in microamperes.
Have anyone tried with InAs TFET simulation? If you are getting same result as they gave in lookup table, pls help me also.
Software Problems, Hints and Reviews :: 10-17-2015 06:42 :: gold :: Replies: 0 :: Views: 593
Ask supplier for s- parameters then add same for traces.
Use lumped circuit analysis
Choose values for trace Ls, Cp to each end point then lookup parameters for vendor model and size for L,C,R.
It will be pretty bad at 12GHz for 805 and many 603, unless specifically designed for RF. (flip chip or wraparound.) Orientation also affect
RF, Microwave, Antennas and Optics :: 09-16-2015 06:49 :: SunnySkyguy :: Replies: 13 :: Views: 1638
hi every one
i have a simple design named "hardenSBox" comprised of two parts 1)sequential part, so-called "regOut" which has 8 DFF 2)combinational part so-called "lookup". i haved showed in following section, verilog code related to each part:
ASIC Design Methodologies and Tools (Digital) :: 08-07-2015 15:22 :: Jupiter_2900 :: Replies: 2 :: Views: 703
FPGA designs are based on lookup tables (and a few other basic elements). The lookup tables are small RAMs, and can be configured to perform a specific logic function after the device has powered up. Connections to these LUTs connects to various muxing logic, which can also be configured after the device has powered up.
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-26-2015 20:18 :: shemo :: Replies: 4 :: Views: 558
Instead of generating different lookup tables during execution - what would make an expressive overhead on core processing - you could consider to simply change the sample frequency for the PWM, but using a single table.
Power Electronics :: 03-20-2015 19:44 :: andre_teprom :: Replies: 9 :: Views: 1185
f(x) can be e.g. implemented as lookup table or polynomial.
RF, Microwave, Antennas and Optics :: 02-26-2015 22:31 :: FvM :: Replies: 14 :: Views: 621
i wan to make v/f control of 3phase acim
successfuly i generate 3 phase sine wave, which frequency can vary frm 1hz to 1023hz
using 3 phase DDS by sine lookup table, timer,interrupt.
now i wana to implement V/F
i attached my program
Analog Circuit Design :: 02-21-2015 06:52 :: mobinmk :: Replies: 3 :: Views: 2210
First you have to convert the scan codes into the binary equivalent of the decimal number using a lookup table. That gets added to an accumulator. You'll need some method to clear the accumulator at the start of a new number. Each time you enter a new digit you will multiply the accumulator by 10 (too bad the number isn't hex) and add in the new nu
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-21-2015 07:54 :: ads-ee :: Replies: 1 :: Views: 797
I need to know how to send saved data in lookup table to audio codec of de2-70 altera kit
line out in VHDL.
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-13-2014 03:51 :: jackobian :: Replies: 2 :: Views: 1099
It may use lookup tables which have the sine/cosine value in a ROM
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-06-2014 12:04 :: sherif123 :: Replies: 5 :: Views: 1879
You seem to have struggled to explain it to us - so helping is rather hard.
I assume with the 4 bit address lookup you've lost some resolution in the lookup values?
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-01-2014 08:10 :: TrickyDicky :: Replies: 2 :: Views: 755
The DDS is pretty simple. If you want simpler, just use a lookup table.
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-28-2014 13:21 :: barry :: Replies: 4 :: Views: 1131