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Loop Bandwith

15 Threads found on edaboard.com: Loop Bandwith

Architecture for 1.2V 50MHz GB op amp

Well it sounds like since you have a supply of 1.2 you must be in 0.18um or 90nm cmos. Is this correct? Also when you say 50MHz are you talking 3dB bandwidth or Gain bandwidth product GBW ( unity gain BW)? Also what type of DC open loop gain do you need. If it is not important I would say in these technologies and with a GBW only 50MHz you coul

Residual Phase Modulation in PLL output frequency

I have designed a 4GHz PLL frequency synthesizer using integer-N PLL chip. loop BW around 200KHz. I have close-in phase-noise(at 100KHz offset ) of about -90dBc/Hz at PLL o/P(measured in spectrum analyzer). I observe a residual PM 0f 0.1 radians p-p at PLL output(measured in modulation analyzer ),this value goes down to 0.02 rad if I sel

AD8017 connecting output to negative input

With a CFB amplifier, the output to inverting input resistor sets the loop gain, almost independantly of the divider ratio. For maximum bandwith, you should use 620 ohms as suggested in the datasheet. With 2k2, the bandwidth is reduced to about a third.

a question on PLL- nature frequency, open-loop bandwith, etc

Hi: What 's the diffrence and relation ship between "nature frequecy", "open-loop bandwidth","open loop bandwidth" and "bandwidth" of PLL ? Best Regards !

a question about pll stability

As we know,when the phase shift at the open loop pll bandwith is bigger than -180+PM,where PM stands for phase margin and is ususlly >45 degree,we say the pll is stable.I am confused that in a second order pll the phase shift in the frequency near dc is almost -180 degree, but we usually don't care about that. How can it be stable when the freque

question about wideband low OSR DSM (hamoui's paper)...

does somebody had read Anas A. Hamoui's paper "High-Order Multibit Modulators and Pseudo DWA in Low-Oversampling DS ADCs for Board-Band Applications",ieee trans. on C&S,Jan,2004 in this paper, he claims that the best placement of the compled-conjugate zeros of NTF is about at fbw*^(1/2) fbw: bandwith,L:loop order but i fi

How to determine the capacitor size for SC-CMFB?

hi friends: Can somebody tell me how to determine the capacitor size for SC-CMFB? does it decrease CM loop bandwith ? thanks in advance

The relation between 3dB bandwith and input freq. of opamp

Basically 3db bandwidth tells you at which input frequency the op amp loop gain will be half of it dc gain

How to determine the loop bandwith of PLL?

frist of all u need to study the PLL as a system well , and check by urself how the LPF will affect the loop , then u should know ur application well , demodulation , FS , and so on , to see if there are any constraints on ur filter bw or not , and then begin ur desgin khouly

How much phase margin is needed for a fractional-N pll?

Actually , The frantional-N designis the same as general PLL. Just You must care spurious tone that you can accepted . Nornal the loop- bandwith is lower for filter the spurious tone.

Current control loop bandwith

What must be the low pass filter's lowest cut off frequency of a current measuring circuit for a 500us current loop? Is 2 KHz enough or is 4KHz needed?

relationship of bandwidth of CMFB and signal loop

Thank you, Tata, But what I mean is that for a robust circuit, the bandwidth of CMFB should be larger or smaller than that of the signal loop. For example, if we design a fully-differential opamp with the bandwidth of 20MHz, then how do we choose the bandwidth of its CMFB? how large is the value for the well-designed opamp, 10MHz

Question about PLL synthesizer

HI :roll: :idea: Liberal, Your design is not good . If you have frequency which you want and voltage is in possible range (for example with power supply VCC 5V control voltage inside PLL loop is between 0.5-4.5V) PLL loop is not designed good. Check your data for PLL design or wide or limit loop bandwith. GL XTASA

how to simulate the bandwith of a pll

i think the loop bandwidth will determine the aquisition range of the pll.if u try to reduce the ripple in the vco control voltage by lowering the loop bandwidth and rejecting high frequerny components then the aquisition range suffers.this is because the range of frequencies for which the pll locks is determined by Win-Wdiv

PLL:lock and capture range

The capture range is determined by the difference between the free-running frequency of the VCO, the input frequency and the bandwith of the loop filter. Simply said this difference has to become small enough so that it can fall within the BW of the low-pass loop filter. That is, you sweep the input frequency from let's say 0Hz toward the (...)

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