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19 Threads found on edaboard.com: **Loop Gain Calculation**

suppose any Voltage current feedback network is implemented and we have calculated its Aβ (**loop** **gain**) then how will i found its input /output impedance from this expression . Figure is given below for a reference
I have calculated Aβ as -gm1 ro1 {Rs gm / (1+ gm Rs)}
I can confirm your **loop** **gain** expres

Analog Circuit Design :: 10-20-2016 08:02 :: LvW :: Replies: **9** :: Views: **1758**

Hello everyone,
I have to design a fully differential amplifier design. I have been given the following specs, How to calculate the **gain** and bandwidth of the amplifier:
The given specs are:
1)Close **loop** **gain**
2)Max Input Step
3)Max **gain** Error
4)Max Settling error
5)Max Settling Time
6)PSR
some other (...)

Analog Circuit Design :: 08-21-2016 06:45 :: niteshtripathi :: Replies: **2** :: Views: **1278**

Hello The attached is a power supply involving eight current mode (CCM) bucks all in parallel, driving into the same load.
Its easy to get the Feedback **loop** bode plots (& calculate **gain** and phase margin and crossover) for one buck supplying into one load, but how is it done for eight in parallel?
Vin=28v
vout = 1v5
iout = 136.8A total
Eac

Power Electronics :: 06-08-2016 20:05 :: treez :: Replies: **13** :: Views: **784**

Its interesting, that oscillation will occur where the overall **gain** plus phase produces maximal feedback around the **loop**.
For various reasons the transistor plus its parasitics may contribute some extra phase delay around the **loop**, which can pull the frequency.
Another gremlin may be that the inductor has a core material that has a non (...)

Analog Circuit Design :: 04-24-2016 01:14 :: Warpspeed :: Replies: **11** :: Views: **964**

The error amp is only part of the overall open **loop**, as you know.
But yes you need to find the transfer function of your one above, it is Zfb/Zin....use complex numbers to work it out.
So you need the Power stage & modulator small signal trxfer function
Then you also need the error amplifier small signal transfer function.
Then multiply

Power Electronics :: 03-31-2016 12:39 :: treez :: Replies: **3** :: Views: **1588**

From the datasheet TL431, Fig 21, I see that dV(KA)/d(Vref)=1+(R1/R2); they are using an op-amp model for the **gain**. This equation is given in the Fig page 18.
This would be the closed **loop** **gain** in a zener reference application but the application note in question specifically refers to the TL431 open **loop** (...)

Power Electronics :: 02-29-2016 14:29 :: asdf44 :: Replies: **8** :: Views: **1099**

Talking about an exact solution, you'll derive the circuit **loop** **gain** and determine the L range for that the Barkhausen oscillation condition can be fulfilled. Deriving the exact **loop** **gain** in a hand **calculation** is rather complex, even with a circuit simulator it's not really easy.
A more practical (...)

Analog Circuit Design :: 03-28-2015 10:25 :: FvM :: Replies: **3** :: Views: **723**

Hi all,
I am studying the concept of phase margin. I understand the meaning but I have a question related to the **calculation** of the phase margin in paper.
For example if I have a open **loop** system a(s) = 10 / ( (s+1) * (s+2) ), the phase margin in Matlab is approximately 55 degrees. So closed **loop** system is stable but I want to verify (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 01-13-2014 16:40 :: biolycans :: Replies: **4** :: Views: **1684**

Hi.
I designed a folded cascade Opamp with Hspice and I want to simulate it.
I want to calculate dc open **loop** **gain**, Bandwidth, Phase margin.
How can I do that? please help me.
regard.
A.Jafari

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 11-18-2012 10:42 :: A.jafari :: Replies: **2** :: Views: **1376**

Hi
When I simulated the open **loop** **gain** for a differential amplifier (using NMOS and PMOS transistors), the **gain** and output resistance values are much lower than hand **calculation** result.
Why is there so much difference between the simulated result and calculated result/
Is it possible to manually edit model library file (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 10-06-2010 22:23 :: bejoynp :: Replies: **1** :: Views: **726**

The 0.65V voltage drop across D4 is reduced by the open-**loop** voltage **gain** of the opamp which is about 200,000 at very low frequencies and at DC.
So a 2V input peak is reduced by (0.65V/200,000=) almost nothing so the output is 2V.

Hobby Circuits and Small Projects Problems :: 01-18-2010 17:07 :: Audioguru :: Replies: **1** :: Views: **3923**

hi all.
do i have to design the **gain** ang PM of a cmfb circuit? what to do with stable open-**loop** but unstable closed-**loop** circuit?
thanks in advance.

Analog Circuit Design :: 10-04-2009 11:24 :: ella1923 :: Replies: **1** :: Views: **1027**

Hi all,
I'm puzzled about how to choose the GBW of the pre-amplifier of audio amp, whose close **loop** **gain** is 1.
By hand **calculation**, to keep close **loop** frequency response identical between 20Hz~20KHz, I think 600K GBW is enough, but the products of TI/NS have GBW more then 2MHz, some even reachs 10MHz.
Thanks

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 08-19-2009 09:17 :: copoler :: Replies: **1** :: Views: **1380**

Hello t_maggot,
I think that you'll **gain** nothing, because the increase of current is the consequence of the control **loop** action: The speed decreses, so (SP-PV) increases commanding more tension (or more current if your power driver uses current feedback).
I think that you must think in the delay introduced by the speed **calculation** from (...)

Robotics and Automation Forum :: 12-22-2008 12:53 :: jorgito :: Replies: **3** :: Views: **1618**

It will be 50mV/20 at the output at that frequency where PSRR is 20. Calculate the input offset by dividing this by the closed-**loop** **gain**

Analog Circuit Design :: 11-18-2008 04:01 :: saro_k_82 :: Replies: **2** :: Views: **1505**

-180 deg is same as 180 deg. It's 360 deg difference.
Hi, I have some question here regarding phase margin **calculation** in feedback **loop**. Before this in my circuit design, i always see that my phase start either at 180 or 0 degree, so that at **loop** **gain** at unity i always get phase margin from 60 to 100 degree. But for this (...)

Analog Circuit Design :: 10-26-2006 06:12 :: isaacnewton :: Replies: **4** :: Views: **1512**

You need to do an open **loop** **gain** **calculation** and do a Bode plot. From this you can determine what changes you can make in the **gain**s and pole-zero frequencies.

Analog Circuit Design :: 04-11-2005 15:33 :: flatulent :: Replies: **10** :: Views: **1407**

Hi mike_bihan,
when a feedback circuit is analyzed, the load effect of the feedback network must be included in the **calculation** of the open **loop** response. The feedback network affects both the input and the output of the open **loop** transfer function. This is readily considered suppressing the feedback at the input for looking at its load (...)

Analog Circuit Design :: 03-30-2005 15:35 :: zorro :: Replies: **5** :: Views: **2298**

as you know, when we calculate the **loop** **gain** we set the main input to zero at first.(P249 in the book "design of analog cmos integreated circuits" by Razavi). i want to calculate the **loop** **gain** in a switching power supply. the output voltage is constant. but what is the main input in the switching power supply system? the (...)

Analog Circuit Design :: 10-11-2004 03:04 :: achilles.wang :: Replies: **2** :: Views: **1408**

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