Search Engine

30 Threads found on Loop Xilinx
Hi bro. I have 2 questions, please answer me. 1-Why sometime for programming of microblaze in xilinx fpga use while(1) loop and sometimes dont? see below code for example... I want to generate a PWM signal using the Timer/Counter IP Core. Nothing shows up. What I did: Added the core, connected the PWM0 port of the core to an ex
Dear all please tell me is there any alternate for 'for' loop in verilog. i am using xilinx. please explain me how?
signal dff_chain : std_logic_vector ( n - 1 downto 0 ) ; process ( clock ) is begin if reset = '1' then dff_chain <= ( others => '0' ) ; elsif rising_edge ( clock ) then dff_chain ( 0 ) <= input ; for index in dff_chain ' range loop dff_chain ( index + 1 ) <= dff_cha
Assuming you're only simulating it - somewhere appropriate in the process. In simulation, processes without a sensitivity list loop forever in 0 time. You need a wait statement to make it wait to move the time forward.
Hi, I've got some errors by synthesize a verilog code. I've googled this errors but I couldn't find a solution. Can someone help me ? For the code block below, /*8by8'lik alt bloklarin uyum toplamlari elde ediliyor*/ reg sum_8by8_q; //There are four 8by8 sub blocks reg array_1D_sum_8by8 ; //2 rows reg
There are no line numbers in your listing, which makes it a little difficult, but here are a few comments: 1) Don't use IEEE.std_logic_arith.all, use ieee.numeric.std instead 2) (0 downto 32) is wrong, what you mean is (32 downto 0) (or maybe (0 to 32) But your main problem is that the for-loop has to be inside a process.
HI, when I have FSM, I can send via UART 1 byte in one state and then go to the next. But if I'd like to send data signal containg e.g 40 bits, how can I do it in some loop, instead of creating 5 states (one for sending signal(39 downto 32), next for signal(31 downto 24), ...) ? I can some counter from 5 to 0 but how to load appropriate part of si
i am using the multiply and accumulate IP core from xilinx ,the operation it performs is first multiply the two inputs a and b and give prod= a*b then it subtracts the previous output from Prod s=s-prod problem: i m not able to see the s(present) output as it is loop back. in chipscope one of my input is 30Mhz (12 bit samples) and other one is a
hi friendz... i am newer to verilog desgin.while simulation of my verilog code in cadence it find the infinte loop design. so that i couldn't get the simulation result .but in xilinx i got the result for that design..... can you help me for the same...
Does xilinx XST support VHDL textio library for synthesized code? Most likely not. P.S.: If it's for a simulation test bench, the sequence would be for i in ar'range loop readline(f, inline); read(inline, ar(i)); end loop;
run trce with the correct FROM-TO constraint? keep in mind that you might need to pass PVT conditions to trce to get the min/max delays. the LUT's don't have the same closed-loop calibration that the IODELAY's have.
HDL attempts to generate hardware. You have defined a combinatorial loop. eg: assign x = x +1; makes no sense as a combinatorial circuit. It will work as a sequential circuit. eg: always @ (posedge clk) x <= x +1;
You can also think about using some tools integrated in Matlab, as xilinx System Generator, that allows you to get your hardware in the loop. Working in this way your can use Matlab for data injection, your HW for running the algorithm and once again Matlab for collecting data output and performing the validation. There is a JTAG connection bet
hi,i'm working with that hw in loop co_simulation in matlab xilinx system generator and i encounter an unacceptebale error that"s (("Illegal Period, This blocks attempts to set period that is a non-integer multiple of the system rate Error occurred during "Block Configuration" Reported by: 'figgg/puls/puls'. .that is not a non _ integer mult
Thats what I was expecting, glad you stated it explicitly! Assuming you'll be targeting xilinx devices. It has what you call Delay Locked loop(DLL), instead of PLL. To utilize DLL in your design you have to generate and instantiate HDL module in you design. xilinx core generator will take parameter like multiplication/division factor (...)
hi, Spartan3e starter kit has JTAG USB interface for fpga programing, and debugging.... I want to use it for high speed data transfer interface from PC to Board... reading big data buffers....RS232 would be to slow. i found this System Generator for DSP: Performing Hardware-in-the-loop System Gen
If it is during development that you need to communicate, then use MathWorks MatLab Simulink with System Generator. Then use 'hardware-in-the-loop'. Some document about this:
Hello. I'm working on a "all digital" PowerLineCommunication (PLC) project. Destination chip is xilinx Sparan 3 FPGA. This is my first (real) communication projekt and I'm a little stuck :( I searched the internet for all Costas loop information available. But most of them just provide basic information about the loop (basic (...)
To my knowledge While loop in Verilog HDL is not synthesizable. So it is not used in RTL design. Its only used for verification puposes.
FOR i in (WIDTH-1) TO 1 loop where WIDTH is INTEGER :=5 The loop does never terminate... write (WIDTH-1) downto 1 instead of (WIDTH-1) TO 1 i'll give you small process to check it... process begin for i in 5 downto 1 loop report "this is " & integer'image(i) &"iteration"; end loop; report "i got out