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11 Threads found on edaboard.com: Low Noise Amplifier Cadence
Hi, Well I have to design a low noise amplifier for ultra or narrow wideband applications. which simulator will you recommend considering I have to use multi gate mosfets. I don't have cadence or mentor graphics license so, Which is best free simulator out there? technology for LNA is 32nm since it will be (...)
hello I am simulating low noise transconductance amplifier circuit in cadence virtuoso and for the transient analysis I am getting the output current as 10 microampere when the input is fed at 2.4GHz and when ac analysis is done then the output at 2.4Ghz is showing as 10.339 mA.I could not understand the concept. Can (...)
I designed an lna,the input-referred 1dB compression point is shown below 76307 With the increase of input power, the LNA gain increased. I think the input-referred 1dB compression point is very strange I feel normal as follows, 76308
I have designed a low noise amplifier and gotten the satisfied simulation results when it was simulated in ADS. Unluckly, the simulation results in cadence(ic5141+mmsim610) is very bad. The paraments are all the same. The difference is that the PDK in ADS is TSMC rf cmos 0.18um v5 and the PDK in cadence is (...)
... I'm designing a low noise differential amplifier using the ams0.35um technology in the cadence environment. This amplifier is going to work as a differential amplifier without feedback because the amplitude of the input signals is really small. The output is going to be single ended. (...)
now, i am doing a project about a wideband low noise amplifier. but i haven't any tools,i only know that cadence'spectre can doing this ,so is there any others can doing this ,i have hspice in my pc ,so i ask whether hspice can doing this .and how to set the parameter to simulate the LNA.
Hello, I have designe a low noise amplifier, but I don't know if my procedure is correct, is there someone that can help me? in attached there is the circuit. Thank you
Hello, I have a great problem...I have to design a low noise amplifier , who has the following features: 1)V DD = 3V 2)Zindiff = 200Ω (RSdiff = 200Ω) 3)I BIAS = 5mA 4)f 0 = 1.8GHz 5) All the transistor should have minimum legth -I have to use a differential amplifier what can I do to (...)
I repost this question. I am using IBM 0.18um BiCMOS process. For cadence schematic simulation, I used a bipolar transistor(BJT) for low noise amplifier design and simulated in DC analysis. BJT is always working in region 1 or region 3. I am so wondering region 3 is saturation region or breakdown region. I (...)
For cadence schematic simulation, I used a bipolar transistor(BJT) for low noise amplifier design and simulated in DC analysis. BJT is always working in region 1 or region 3. I am so wondering region 3 is saturation region or breakdown region. I attach the picture for your consideration. Thanks
I do not know for cadence but is this an RF question based on your figures posted in analog forum. I know you want a limiting amp but this is treated under the low noise amplifier Dersign section of any RF book. See if any book in RF covers cadence and I think cadence must have some (...)