Search Engine www.edaboard.com

Low Power Technique

Add Question

34 Threads found on edaboard.com: Low Power Technique
i am working on leakage power minimization of 4 bit CLA but many of the proposed methods are not working well with circuit. 1. upon applying diode connected power gating the maximum output is 600mV that should rather be 1V. what should be the reason? 2. when added only footer network the response degrades.
HELLO i am new member,i have a project about Design of two low-power ful ladder cells using GDI structure and hybrid CMOS logic style in my university and i have probelam with designing of this circuits in Hspice. 1:I need 90nm and 0.13um cmos technology library for hspice 2:I do not know how does the ulpd circuit is design and where does the
Hi All, I want to implement 7-128 decoder using one of the low power technique,Stack technique. As I am new to VLSI domain,in order to implement the same, what are the pre-requistes needed? Thanks in advance
My focus is on MAC unit to reduce its area and power dissipation.I'm planning to code multiplier unit by using vedic or any other technique. Can anyone suggest a good modification on this MAC unit? thanks.
Hi, I am comparing Plain synthesis Netlist vs low power synthesis Netlist( i have only used clock gating low power technique). I am using Cadence Tools. i find that there are unmapped points in low power netlist ( Red coloured "U") which is of clock gating as shown in the (...)
When doing low power, why the Isolation cell need to be placed in always-on logic? Thx Kumar
Playing with the stability of a PA is not as simple as it look. First step would be choosing the input and output matching network topology. Usually a high-pass network for the input, and a low-pass for the output, get the best performance in terms of stability. On the other hand, placing any degenerative resistors on a power Amplifier would decre
Hi i am making a project using VHDL and i wanted to use some low power techniques to optimize my design. I have used clock gating already.What are the other techniques i can use? I wanted to implement Multiple Vdd or supply voltages technique. What are the ways to implement it?? I have heard about (...)
Here are some low power techniques. 1. Architectural Level: Pipelining and asynchronous. 2. Design Level: Multi VT, clock gating, power gating, multi VDD and DVFS. 3. Process Technology: Silicon on Insulator, multi VT, Body Biasing, FinFET. Search in google to know details of each technique .
Hi All, I'm trying to implement Muli-Supply Voltage technique to a design. Basically, in my design I've two analog blocks operating at two different voltages, and I've attached a level shifter b/w the two. I've specified voltage of primary power net as 1.5 V for the first block and 1.8 for the second.So, now when I extract power (...)
hi all, i was reading paper "A low power Pipelined ADC Using Capacitor and Opamp Sharing technique With a Scheme to Cancel the Effect of Signal Dependent Kickback" IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 9, SEPTEMBER 2009. i attached this paper. I doubted the cap sharing technique. 1. since the thick and thin (...)
... I would need a start up circuit. Does anyone know a paper that implements these technique? Perhaps this paper may help you?
Hi, While scan stitching how I come to know that scan stitching to be handled with low power technique? If I simply stitch all the design flops in a allocated scan-in and sca-outs but this has to be taken care with low poer techniqe. How to handle such scenario? Please any one clarify / describe on this. I am very new (...)
If your library has power switches and isolation cells , you can follow "low power Synthesis Flow" of Synopsys Design Compiler to power gate each section of your design. You must refer to "Synopsys? low-power Flow User Guide Document. This (...)
sir, i am designing lna for low power.please provide me some idea of the new technique that i can adapt for my research work.
What's the best SRAM configuration? (4T, 5T, 6T, etc). I am designing an SRAM with low power and low leakage in digital implementation using Verilog coding (VCS simulation). Also, what's the best technique I can use to minimize the leakage? Thank You!
hi sir, i want to know about recent technique in the design of low power LNA for wireless communication application with respect to do Phd thesis work. now only i have applied for Phd and iam in need some suggestion and guidance to proceed further.
Since this is a low power situation and the frequency range is 4:1, you can use a transformer type method.
Currently I am doing the Transmitter equalizer design and my focus of the area is low-power 2.5Gbps transmitter equalizer. I am not sure which mode should I use for my design, either Current mode logic(CML) or voltage-mode (VM) driver. Can anyone tell me which one is most suitable to use for low-power design? I see that (...)
Domino circuit and low power don't get along with each other.