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28 Threads found on edaboard.com: Lvpecl
I have a RF switch that I would like to select between two clocks (125MHz and 150MHz). The clocks are both lvpecl signals, 100ohm diff pairs. The SP2T inputs are 50ohm single ended. Can I use a balun for the Diff to SE transform? What kind of termination would I need on the diff pair side? 100 ohm resistor? W What is going to happen to the s
118100 This is the standard to convert lvpecl to LVDS termination. I am confused here to see the voltage divider of 10k and 10k only on one line. Shouldn't this divider be present on the upper line also? Thanks in advance.
I am using Dflipflop MC100EP31 and producing a ns pulse.Its ouput its lvpecl.I am interfacing it with a rf amplifier i connected the output of d flipflop to an ac coupling capacitor (1nF) and the output of the capacitor is connected to the rf input of this the proper way to connect input?
Use lvpecl std oscillator for reference clock.. Regarding frequency:Try to generate SATA core using Xilinx Core generator to get the supported ref clock frequencies..
Hello, I need connect comparator ADCMP562 with PECL compatible logic output with lvpecl 3.3V input on Sprartan3A. Can you help
Start with this.................. Fully Integrated Wide-Range, Low-Jitter, Crystal-Oscillator Clock Generator High-Performance Clock Generator 10.9-MHz to 1.175-GHz Frequency Range Differential Low-Voltage Positive Emitter-Coupled Logic (lvpecl) Output
There is a driver in my circuit which is the lvpecl output, I use the AC couple between the output and the reciver. It was konwn that output should connect 200 ohm resistor to the GND before the coupling capacitor to provide 14ma current for the OE output. Since it's 1:10 driver,and each differential output should connect 200ohm resistor,I was w
Hi all, I need to design lvpecl and LVDS for output driver, but even never heard of those before. I checked wiki and some app notes, but can't find out more detail information. Can someone show me more reference materials? Because based on those schematics (ex. TI app note), the design is pretty straight forward. Thanks a lot...
ECL gates can be operated as comparators if you don't mind low gain and maybe some asymmetry from the not-balanced- differential signal you describe. If your input signal is continuous (like a clock) then a capacitor level shift might do. Or if it has a guaranteed minimum transition density like 8b/10b. You might check whether one of
HI I am using a LAttice FPGA which needs a SerDes clock of CML level while my clock IC can supply only lvpecl . How can i connect the two of them PLease help
I've created schematic using single CLK input. Then I've changed the input using ibufgds primitive (naturally inputs were renamed to clk_p and clk_n) Now I want to modify timing constraint to reflect changes. But still there is only clk net available. Moreover there is only clk pin available during floorplanning. Does anyone know why? robert
Can you clarify which type of ECL you have? For example 10K and 100K ECL have negative voltages, and won't interface directly to the FPGA. However, if you have positive ECL, then you may be able to use the FPGA's lvpecl I/O standard.
Hi On my PCB, I got a ethernet PON SERDES that connect to a Optical Module(OM) via lvpecl interface. 1.25Gbps, 130R + 82R Resistors DC terminated at Recieve direction And there is 5 OM available , 3 of which are the same type of brand H , while the other 2 are of brand F. Now, only the specific one OM of brand H is working well on board, wit
Hi, I am using a TI CDCM7005 pll and a Crystek CVC55CW vco, How to connect the output of the VCO which is CW 1to 5 dBm output to the input vco signal Of the pll which is lvpecl logic? There is a pin named VBB in the CDCM7005 which supply VCC-1.3 volt that might help to do the translation. (datd sheets are attached) thank you all
Hi... I am designing high speed transceiver on PCB, which has ADC signals which are interfaced to Spartan 3A FPGA at Bank 3 by lvpecl standard. This interface works at 250MHz. Signals from the Bank 1 of this Spartan 3A FPGA are interfaced to I/O of Spartan 3 FPGA. These signals works at 125 MHz. Presently these signals are at LVCMOS_3V3 standard.
Hy, Is it possible to get 2,5GHz smd clock oscillator with cml or lvpecl output? I do not want VCO, but stand alone oscillator. On Fox electronics I saw they offer different oscillator but the highest frequency is around 1,3GHz. Thank you very much for help in advance,
XTAL based oscillator on 7th+ overton, multiplied to your frequency. Sinewave to lvpecl or any other appropriate levels using high-speed low-jitter logic device (I would recommend ONSemi's NB7L216). What is your desired clock rms jitter value?
hi What is the standard for lvpecl interface?
Does anyone know why lvpecl interface do not care its output impedance 50 ohm to match 50 ohm transmission line?
3.3V lvpecl DRIVER TERMINATION