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20 Threads found on Mac Unit
Hi All, I have a 2 questions 1. What are the most critical maths you need to know when going for a DSP + FPGA interview ? , e.g multiplying 2 N bit numbers will take up 2* N bits. 2. How many bits are needed for a mac unit ( say you have two 16 bits inputs to a multiplier which goes in the a accumulator of 40 bits) . I dont understand how t
i know that initially it's value will be z. but this makes my mac unit not to add and accumulate. the adder is adding the multiplied result to the wire whose initial value is z. what should i do? please help me. thanks.
The below diagram is the parallel mac structure. In parallel mac both partial product addition and accumulation take place at same time. 110921 The partial product summation + accumulation unit of above parallel mac is given below. 110922 My problem : When I give input to multiplier as
The below diagram is the parallel mac structure. In parallel mac both partial product addition and accumulation take place at same time. 110319 I want to multiply 5 and 3.(both are 8 bits) The 4 partial product I got from modified booth are p1: 0000 0101 p2: 0000 1010 p3: 0000 0000 p4: 0000 0000 I cross checked
My parallel mac unit design is given below. 109108 I have codes for accumulator , booth encoder..etc Now problem is how to combine this in parallel? can anyone help. ieee paper is attached below. 109109
My focus is on mac unit to reduce its area and power dissipation.I'm planning to code multiplier unit by using vedic or any other technique. Can anyone suggest a good modification on this mac unit? thanks.
Fact - one of the most important hardware blocks in DSP cores is the mac (multiply accumulate) unit. Assumption - the simple "shift and add" algorithm is too slow and therefore isn't utilized. Question - what is the most common algorithm used today for implementing modern mac units ?
The A and B matrices should implement have 4x5 and 5x3 dimensions.. It has to pipelined and parallel. 1) Implement the code with integer type signals with test bench. 2) Implement the code with std_logic_vector type signals with test bench. I understand the logic for this code but I have no clue on how to code it. :???:
Been looking for a good explanation on mac operations but I found nothing that satisfies my curiosity. I get the point that in DSP processing mac units are required but that is about it. I was looking for a lower level explanation of the mac unit and operations. I kept on finding documents/white papers (...)
Hi All, Anyone know about the advantages of Partial Product Multiplication over normal Multiplication?? I have seen some latest publications in which they use "Partial Product" in hardware mac/Multiplier unit. Thanks & Regards, Naveed
Hello! I want to use AM3894 for my new design. Has anybody tried this chip? In short, I need to develop something like small DPI unit. I need to filter Etehrnet traffic (near 40 Mbit/s) and than encrypt it. I need two Etehrnat mac Interfaces, Frequency more than 1 GHz, Linux OS. Thnx.
Hi, I am trying implement a new multiplier accumulator unit (mac) architecture in FPGA. Its quiet fast. But I need an application which utilizes this mac. I need to compare its performance with the usual mac architecture. Give me some application which will push the mac to its limits. Thanks
DSP = Digital Signal Processing and Digital Signal Processor. The first one is very straight forward and the second one is a microcontroler or microprocessor designed for Digital Signal Processing. Most of them (if not all) got a mac(Multiply-accumulate) and sometimes a FPU (Floating Point unit). dsPIC is a DSP manufactured by Microchip.
hello everyone i m doing pipelined mac unit in dsp processor as a rtl model it is pipelined by adding register in between stages indivisual blocks of multiply, accumulation, registers all gives correct simulation output but overall simulation of rtl gives correct output upto product, but does not give correct output of accumulation since it use
i want to know vhdl coding of mac and vhdl coding of look up table.
Hi Folks What is the best rounding precision to be adapted when designing a mac unit (effectively part of a low-pass filter) that will porbably be implemented on Spartan 3 ? .. given that the inputs are 2 16-bit vectors .. My main concern is power saving ..
Hi friends, In mac layer we ar coming towards two words MSDU(mac service Data unit) and MPDU(mac Protocol Data unit).What is the difference between these two? Please help me. Thnaks in advance, Goud
hi, i need a "VHDL code" for signed mac operation.. preferably, a generic code for the same.. or an IP core... can any1 get it.. thanks! /cedance
hi, have anybody incorporated or used xilinx core in ur project?? i mean, i have a xilinx core mac unit but am not able to compile it.. i have my other modules along with the mac code from xilinx core.. (am intending them to be used on xilinx fpga only), but how do i compile it.. there ar some procedures for it, seems. any1 worked on it (...)
Hi, Has anybody tried a 802.11a mac in a FPGA? Can somebody tell me the expected gate complexity for such a core, which Xilinx VirtexII chip may be suffecent??