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17 Threads found on edaboard.com: Manifest
Magnetic disturbance would manifest itself as a purity error and the picture geometry would be twisted. This looks more like the start of vertical retrace isn't being blanked properly or the scan signal is drooping, an electrical fault. Try what Larry suggests, if it isn't that the fault will be in the retrace blanking circuits. If Larry found th
The lightning bolt can be parallel to a run of wiring, and by induction can cause a surge in the wiring. The surge might consist of current flow, or if not then it might manifest as a voltage spike. A parallel bolt is probably the scenario that will cause maximum surge, and most damage. The bolt does not need to strike wiring in order to ruin equi
Hi, I am not against Analog meters. But IMO if you retrofit an analog meter with digital circuits to make it 'smart', all the problems of both analog & digital will manifest with additional problems due to interface (eg: spring forces may change, affecting the accuracy). Anyway if you want to use a smart meter, as you told, the problems do exis
I am interested to know that why do MOS capacitance values (Cgs,Cgg,Cdd etc) calculated from AC analysis deviate from the values calculated by formulae that are present in VLSI books. Simulations are based upon BSIM models. The value they manifest in AC or transient or any other type of simulation rely upon the values of BSIM. When we have those v
I am interested to know that why do MOS capacitance values (Cgs,Cgg,Cdd etc) calculated from AC analysis deviate from the values calculated by formulae that are present in VLSI books. Simulations are based upon BSIM models. The value they manifest in AC or transient or any other type of simulation rely upon the values of BSIM. When we have those va
Hi, I am interested to know how do you tell whether a violation is because of a setup or hold while running ATPG TDL's(patterns). My guess is that if you get mismatches like simulated 1 instead of 0 or 0 instead of 1 is setup and hold's generally manifest as X's. Please through some insight on this topic.
Hi all, I'm facing a very complicated problem wile designing a digital component at the transistor level (RF CMOS transistor). The problem manifest itself when I construct the component using basic gates like (DFFs, MUXs, logic gates...). I thing of inserting buffers to resolve the problem. Could you tell me how many gate to drive with each
When you extract the JAR file, you get to see the "META-INF" folder inside which you have the manifest file. Inside the manifest file, there is a 'Main-class' property which tells you the entry point ( the class that has the main method). It might look something like this... manifest-Version: 1.0 Main-Class: (...)
Hi, Have you studied the main link on that topic? Here it is: All what I understand is that using carbon fiber as a current conductor it is able to manifest negative resistance, just like a tunnel diode has a range in its voltage-current characteristics: when you increase voltage, the current decre
Dear all, If you open a blank project in Delphi 7 or Delphi 2006, and drop a TXPmanifest component on its main form and a TMainMenu. Then run the project, the main menu items will have wrong colors (not XP colors). This color problem in using XP manifest ( XPmanifest ) in Delphi, is known problem. But it is not solved from Delphi 7 (...)
You must account for lot to lot variations and die to di variation on the same wafer. As both kind of variations manifest themselves in the same way you must add them and consider them with a uniform probability distribution. Additionally, you must account for device to device variations (matching) inside the same die and one device close to the ot
When the pfd update frequency is comparable to loop bandwidth. the continious time modelling of PFD does not hold good. And then you have to take the DISCRET (I mean sampling effect) of the PFD. Sampling effect manifest in term of folding of the out of band noise into the pll bandwidht and hence lead to increse in phase noise. Also regarding the
ESD is a form of EOS. EOS as stated earlier is any Volt or Current condition outside a circuits normal operating conditions. The resulting failures manifest themselve as dielectric ruptures (over voltage) or thermal damage (over current/power). ESD typically has a very small amount of total energy available so the damage is smaller and more cont
Hi Guys: It was stated in a Journal that the Noise Figure and Conversion Gain in an Up Cnversion Mixer utilized in the Transmitter topology is not a key parameter due to large input signal. Some arising questions are: 1. If NF is not the key parameter, how does the effect of flicker noise which manifest around 1MHz in this Up-conversion Mixe
Hai, i also need this one. any link pls / Warning - No "me too's" or other useless posts at EDAboard. Rule #2: 2.0 UNUSEFUL POSTS AND FILES While "thanks", "me too's" are strongly unwanted here on EDAboard, as they make unreadable forum contents, you may manifest your gratitude using PM (Private Message) or "Donat
Hi, How does skin depth manifest in modern PCBs. The tracks are not circular in cross section. BR M
I find that FEKO have symmetry bug 8O I'm use example 5. Results are wrong if we change wire to smallest segments( gain is negative and impedance is wrong). I'm change this example so I'm delete symmetry and do that without symetry. That problem can be manifest only with small segments of wire not triangle. Here is changed example.