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158 Threads found on edaboard.com: Matlab Verilog
Attachment is matlab/Simulink pipeline ADC Model.
The software to use for all Altera devices is Quartus II. In order to download it you can use also only the programmer. matlab is not a language in which you can program an FPGA, you need to translate it in VHDL or verilog in some way.
hii... i have matlab,sysgen and xilinx ISE installed on my pc,,, i have 2 files with m on is matlab file and another is simulink file,, i m confued how to convert it to vhdl code? if possible give me detiled procedure... thank you
I am designing a rather high resolution (>15bit) delta sigma ADC. I have a design that's working in matlab and I am trying to build the same thing in cadence using verilog A modeling. Every component I have now is ideal and in verilog A code, so that means no transistors, no resistors and no capacitors. I am using the function laplace_nd to (...)
Any body help me out how to interface matlab model in verilog. The objective is like I have a matlab model which gets the input from the verilog and generates output. verilog needs to use the matlab output for further processing.
Can I use the smic 0.18um lab to model Fowler-Nordheim tunneling effect? If so, How can I do this? Otherwise, how can I model this effect? By using matlab? Maybe it would be too complicated......................
matlab or verilog A? which one is better for modeling the analog system and simulation it.
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All ICs come with a special Compiler. I used CC2430 and using IAR, I burned a C code onto the IC. 8051 ICs use assembly and AVR use C programs. matlab, I really doubt you can burn matlab into an IC
Hello everybody Nice to join this forums. Does anybody has experience with verilog HDL code for Delta-Sigma DAC. I have simulated the delta-sigma loop multi-bits for WLAN with matlab OSR = 4( Oversampling Ratio) BW = 10 MHz ( Bandwidth) The matlab simulation shows that the achieved SQNR for the case of MASH 4th order with 5 bits (...)
Hi, Firstly your have wasted a lot of your time by posting this in the wrong forum. You should have tried DSP / Embeded forum for a much quick and better response, anyway here is what I think about them... 1) Before I write the verilog code, I assume I need to test the algorithm using fixed-point numbers in matlab, right? Tha
use HDL tool of matlab ..ITS POSSIBLE TO READ IN MANUAL
i would design a digital fliter,which is used in a AD chip. I think,first i should design it at behavior level, simulate it by matlab. then realize it with verilog..... i only know such..... what is the flow of the design?anybody give me some suggestion??
Hello, I design a digital filter using matlab and output as a verilog. When i test this digital filter using FPGA, i can see the frequency response for my output signal. But i would like to see the frequency response for digital filter transfer function. What should i do? Thanks in advance for your help.
why you select matlab code in subject? I think if you request verilog code in the subject, you have better results. anyway,take a look at this:
If you want to do system level sim, you can try matlab. For hspice sim, you can substitude the digital gates with verilog models.
take a look at these... CDMA2000 Downlink Simulink Models Simulation of a CDMA2000 downlink system RAKE receiver for DS-SS systems RAKE receiver for direct-sequence spread spectrum systems
i need some sourcecode for EVM test, any language is ok.(c, vhdl,verilog, matlab,verilog-a) thanks
Is it in matlab ---? In matlab you can control the variance.