Search Engine

158 Threads found on Matlab Verilog
Hi all, I have a problem. I am into designing an array of bandpass filters so that it forms a filter bank. I have designed the filter in matlab using fdatool and generated the hdl (verilog) code from's a 6'th order bpf with 3 biquads(IIR Butterworth). pls do let me know that if i can reuse this filter.i.e i am using a serial
Hi all, I have designed a 6'th order IIR BPF(biquad sections) in matlab and generated the verilog code from idea is to have a serial architecture so tat i get an array of bandpass filters. Can any one helpme with the changes to be made in the verilog code to achieve this. I have put the coefficients in a rom file. any suggestions plz c
1. Abstract model in matlab where you insert imperfections and estimated performance. 2. verilog or VHDL model of the digital 3. VHDL-AMS or verilog-A model for the analog 4. Synthesis to get gatelevel verilog or VHDL 5. Schematic design of the analog 6. Mixed verification 7. Analog layout 8. Place&Roue (...)
Is it Baseband processor using verilog or matlab??? may be more details will be better.
Hi, When I run the Smash+Simulink co-interface I get a segmentation fault in matlab. I have 12 inputs and 20 outputs from my verilog code. To narrow down the source of the seg. fault I made the verilog code a simple bit assignment and I still get the seg. fault. Interestingly, when I reduce the number of outputs to 15 (from 20) I do not get a
hi, you can make a iir filter in many differently ways. look at an specific book... like "Digital Signal Processing" by Alan V. Oppenheim and Ronald W. Schafer or look at matlab (release 14 at least) tutorial. There are many ways to do a iir filter in a digital computer. Then you can translate the digital form to VHDL/verilog. if yo
matlab is one thing and verilog is another completely different thing. Each of these are developed to do their specific tasks. I know both very well. If I want to test a fsm generally, I'll use matlab. ( pure software development ) If I'm going to develope a FPGA design or a hardware I'll use verilog. I'll (...)
$fstrobe can export data to a file. use matlab to analysize the data. It will be very easy to solve the problem u met.
Hi I don't that it's useful or not. but in matlab there is a function "resample" that can be used for interpolation. it seems to be possible, if you can convert it (automatically) to VHDL or verilog. regards
an interpretive language is one that isnt compiled. like in matlab you write the script and then run the script and it runs one line at a time and if there is an error, it stops running. but in C you write your code and then compile, which checks the errors and if there are no errors, the linker gives you the exe file. and then you run the program.
Could I get from you matlab coding link for QAM-16 demodulator ?
I have a module based on verilog. I also have input/output data files in term text file. Theyt contain signed integers and is generated by matlab. I want to Simulation my module by using ModelSim like as - Read input file correspond with clock signal as a testbench signal - Simulation by using my module - Write output of my module to other
Can matlab do this job?? And any examples available??
u can fix the co-effiecient values in ROM. to release the channel beheviour. initial channel co-efiecient value's must be get from matlab simulation. then u can update it according the channel variation.
Hello I have done some of this but using verilog-A as the modeling language. For matlab is quite simple, construct the stage with simulink blocks (e.g. comparators, quantizers, gain stages, add nodes, subtract nodes, delays etc.). Then just interconnect all the stages. If you don't have simulink please check this presentations for more info abo
have u tried using the delta sigma toolbox for matlab: and also, do u mind sharing the verilog code? it might be useful to some of us.
Well,any behavioral modeling job involves coming up with the prototypes of all the devices you design. Typical tools which could be used are matlab/Simulink, verilog A. There could also be some other tools which are proprietery. So all the parameters you look for in a design like your IIP3, NF, SNR, etc are actually modelled I hope this solves y
I have got to convert the following matlab code to verilog code as a part of my project work ..Some one plz help me.... /*This function takes in 500X500matrix as parameter and checks for each of the element for zero .If a non zero value is present ,it maintains a count of number of such values as well as maintains a summation of the position(row
There are some books or papers discuss on matlab usage on analog circuit design and related modeling for circuit element such as opamp etc. You can search this board and will find out these materials.
i want to generate a frame ofdm signal to verify my ofdm receiver, are there some existing program to do that? c, verilog, matlab are all ok. if no, can someone provide some generated data to me? thanks