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158 Threads found on edaboard.com: Matlab Verilog
Hi,I am trying to design the timing recovery loop in the QAM demodulator.If i have finished the algorithm design of the loop,then how can i verify my design in the matlab/simulink?How can i get the proper input I/Q data and the right output data,which can be used to verify my verilog implementation? Thanks!
The better is verilog. But if you wish to learn behavior simulation, matlab is better
I never use verilogA or VHDL_AMS for real design , I ever use matlab for analog behavior , but for Mix mode SOC design , in gerneal , analog block design by analog RD , digital is by digital RD , project leader simulation whole chip by hsim/nanosim , but none use beahvior sim in Top level as I know . like Saber , Dolphin smash ..
1. use matlab to gen. a fix-point sin pcm code. 2. in verilog sim test bench. use $readmemh to put the pcm code to a Bus. 3. use waveform viewer to show the Bus data as "Analog".
First you should choose the type you want. MASH or other types. You can read the book first of "JOHNS and MARTIN, Analog Integrated Circuit Design". Then you can simulate the filter in the matlab. Yibin.
I need Gaussian and uniform noise. I can’t use a function because I need to put it in a FPGA so I need to make it out of basic math (+, -, * etc..). I’ve used the matlab noise generators and they work great. You can use LFSR (Linear Feedback Shift Register) to produce noise in certain band. For
hi friends i wrote FIR filter and adaptive filter code in verilog i wanna test this code using matlap 7. i read articles from mathworks web. they said we can interface simulink and modelsim. if any one has already experience in this area. pls help me. i wanna know my code is functional and logically correct. is it possible i can put ADC ->MODEL
Well DSP requires a high level modeling usually done with matlab an ideal solution is ACCELFPGA wich is basically a matlab language compiler . Otherwise .there are plenty of libraries of cores they produce VHDL most of the times and verilog too the HDL code produced by COREGENERATOR,SYSTEM GENERATOR .SYSTEMVIEW and others are well optimize
vsim first u have to call this function,then vsim('PropertyName', 'PropertyValue'...) starts and configures the ModelSim simulator (vsim) for use with the matlab and Simulink features of the Link for ModelSim. The initial directory in ModelSim matches your matlab current
It depends what you want to simulate or modelling: Digital: SystemC, verilogC C/C++ VHDL/verilog (Modelsim, LDV) Analog: matlab (for very complex systems like receiver with rf frontend, sigma-delta converter, baseband processor) C/C++ complex and difficult to read for other designers, but very fast AHDL/VHDL-ams
How do I save data of the simulation result in cadence so I can export to matlab or excel? And where is wavescan in ADE? If the simulator supports verilog/veriloga, you may use verilog/veriloga module to sample the outputs and write to a text file. If you want to write the Analog Artist wave data to (...)
you may first try to figure out ur parameters in matlab/systemview/spw or sth. To design a filter is simple in concept, convolution, piles of multiply-add operations. You may also read some papers discussing different architectures of FIR implementations.
you can use matlab/simulink .. and accelchip ($30,000 solution!) But otherwise you can use java .. and xilinx's forge .. you can simulate in a java virtual machine and later compile with forge.
Dear All : Does any have experiment do sigma-delta Pll ,Does any one have the behavior model ,like matlab or verilog-A . Or other document or scehamatic ? Thanks sigma delta PLL use in RF frequency synthesis ???
I did my graduate thesis about Neural Networks Embedded FPGA. Do anyone want to share docs about it? I used matlab and verilog HDL to design my Equalizer....
Anyone can guide me how to design a Digital Delta-Sigma Modulator ? First order or secomd order will be ok ! I have no idea to build a matlab model for a multi-bit feedback Delta-Sigma Modulator ! After build a matlab model , how to program an quantizer by verilog ? Do i just ignore LSB ?
I'm interested if anyone did this in verilog. I have some C, C++ and matlab versions bat interested to obtain HDL version.
SPW is a system level simulator, something like matlab (although it is more powerful than matlab). It also can used for generating synthesizabel code considering its design rules in system level design. Also it can link to some major HDL simulator like verilog-xl, nc-sim or vcs for direct co-simulation. It has also capability to use (...)