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17 Threads found on edaboard.com: Max Transition Time
Hi, I think it doesn't solve the problem but it reduces the error to max 1 LSB. Klaus
Hi guys, I am trying to place and route a digital design. During the pre place time analysis, the software (Innovus) issues a warning alerting that the slew rate of the several cells is out of bounds with regard to the value specified in timing lib. The weird thing is that I am specifying a maximum slew rate (max (...)
Hi, I want to measure max delay of a full adder,So I use .measure for compare the max of inputs to outputs Rise and Fall times in group of two, but there is negative value in several rise or fall times! .measure tran delay_ar_C TRIG v(A) val='Supply*0.5' td=5ns cross=1 + TARG (...)
hi can any one tell me what's are max transition and max capacitance and how we can juge if they are good or not !!! thanks
Hello Can anybody please explain the difference between set_max_transition and set_input_transition constraints?
What do you mean equal? transition, is the time needed to the signal to goes to zero to one or one to zero. Load, is the capacitance seems by the output pin of the std cell. Both are used in the liberty to characterize the timing, and the maximum constraint should not be violated, because the timing will be extrapolate, and we don't know if (...)
Guys, One question. If you do some new design, how to decide max_transition constraint for synthesis and place&route/STA? Is this something based on experince or there is a right way to decide the maximum allowed value for transition time? Thanks in advance. Hi: As "phoenixpavan" as said, there is (...)
Actually, for each design(EDA), We often set the DRC rules, ie. max_transition max_fanout max_capacitance... You can find "max transition" "max_fanout" ... in a library (.lib synopsys format) If you dont set a "max transition" in (...)
Hi All, On what basis max tran rule is defined? Is it same for all the nets? How is it different and why ? Should we fix all tran violations in the design? Regards Tachyons
hi guys , i have an elementary question about transistor , how can i know the bandwidth of the transistor ? in the data sheet i just found "transition frequency" which didn't have a max value , or it is just the inverse of the "storage delay time" tsd?
One more reason of fixing max transition violation is that bigger transition will result in bigger DC power consumption
Depends on the logic you can ignore those violations but some times it matters... For example you have some combo logic between two different blocks and you are assuming that the logic is going to take time less than 1 clk cycle.. but for the worst case it may takes more than that and this reports to max transviolations... this can be (...)
The max violation may cause large short circuit power since both PMOS and NMOS would be on for a longer period of time.
max skew means the difference between the clock arrive the cloest and furthest register. transition time: decided by the drive capacitance of the cell. Both them can impact the performance of the chip such as the highest working frequency
Hi , I would like to know the causes for the max transition time violation ??? I heard that two reasons may lead to this violation 1) input delay of the pin is very high ( more than ) the set value in libary 2) do the wire length that leads to the delay. I would like to know in each case how (...)
But if i remove enable, than setup control inputs. Wait for max transition and setup time, and than set enable high?
For a non-linear delay model library, the output transition is a function of input transition and your output load. therefore if you define your input transition time and the output load your design is driving, then, there is no need to change_maximum transition which is already defibed in (...)


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