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Mdac Pipelined Adc

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30 Threads found on edaboard.com: Mdac Pipelined Adc
Hello Everyone, I am designing 12 bit pipelined adc. I am facing problem to get the accurate gain of 2 from the designed mdac when I use the capacitors from technology library. When I replace the CI and CF capacitors with the ideal caps I get accurate 2 gain when I check the residual output of each stage, also INL of +-0.5LSB and also no (...)
Hi I am working on a pipelined adc 1. I have built an ideal system that gets an ENOB of 7.99 2. I created a Folded Cascode amplifier that settles in 3ns with GBW 200MHz and Gain 61dB and put it into the system then i got an ENOB of 7.8 but now i am trying to replace the DAC and the switches with real components however i am facing very st
HI I am working on a 4 bit pipelined adc . I am using two 1.5 bit stages and one 2 bit stage with a flash adc . The two 1.5 bit stages include sub-adc , sub-DAC and mdac . I am using one SHA at the input . I ran different simulation . First I tested the 1.5 bit stage independently . With real blocks and its (...)
Hi Can anyone help me or give me proper directions to design 2.5Bit mdac in cadence (90nm CMOS)? I need help starting from the ladder voltage generation.....
Hi guys, Just come up with a strange issue with mdac design in pipelined adc. It is a flip-around 1.5bit/stage mdac with op-amp sharing. I applied DC input so that memory is not an issue. The gain loss I observed is that gain is 1.984 instead of 2.0. With op-amp gain at ~500, I should be able to get ~1.996 (...)
Hi, We have designed 14 bit pipelined adc, which is working up to 120MSPS at schematic level. But, after post layout, I see a settling gets delayed in mdac (gain of 4) output. I see the dip before raising or very under damped behaviour. I found OTA layout causing more than 1.5 pf extra parasitic capacitance in layout.
since i cannot use the bootstrap switch every where as it occupies larger area ...i am trying to implement a transmission gate switch ..but as the input signal level varies the switch is unable to mantain its specified voltage.... How to solve this problem... i even tried with nmos and pmos of higher widths...
Hi ,I?m designing a 14bit 100MS/s pipelined adc (1.8v 0.18um CMOS) and need to an OTA(for front end T/H and mdac of first stage) with this minimum requirements DC gain:96dB and Fugbw:662MHz with CL=10pf(CS =6.6pf)my main question is that how much margin must be considered in OTA design(how much DC gain and unity gain band width??) due (...)
frnds i am simulating mdac stage in pipelined adc........ The output waveform is shown The DAC's functionality is working fine but when you have a close look at the output waveform you can see the negative and pos
hello frnds! plz help me out.....i am struck with a chronical doubt..... i am trying to simulate mdac stage in 1.5 stage of pipelined adc. The schematic i am using is shown in The designed op amp specs are 1.open loop D
Hello ...... I have a Problem related to Fully Differential pipelined adc Implementation. I have Problem in mdac Section Only. I have chosen SC mdac topology to implement 1.5 bit mdac.(Plz see attachment named "differential mdac from Paper" attached) I have big doubt while implementing (...)
I was designing a single ended mdac ie the + terminal of opamp i am giving to a 500mV voltage. My VDD is 1V and VSS is 0. The mdac is in inverting amplifier configuration with a gain of 2. When I am giving hold values(the sampling input) higher than 500mV( ie the Virtual ground) then the mdac is giving the right answer. But when I am (...)
hi,there I am designing a mdac for pipelined adc. The structure of it is plotted as attachment. My question is how to simulate the closed-loop gain vs phase of this schematic because it is a switched-capacitor circuit and decrete-time applied.Then,how does spectere do with its stb analysis with this circuit type?And I only need to add a (...)
I have some problems about the mdac circuit. The output values of mdac should be stable in some periodes. But the output values in my design alwayes have peaks. And this will cause the following comparators fatching wrong values. Can someone tell me what's the problems in my designs?? Thanks!!!!!
I am designing an mdac for a pipelined adc. I am having a problem with verifying my OTA design. The input transistors of the OTA need some bias voltage to operate at saturation. I know the required range of bias voltage needed. The problem is that this OTA is connected in a capacitive feedback. I want to simulate the OTA properties while it (...)
Abo's thesis is a good reference for pipelined adc designs. Start with the mdac in stage 1. Use ideal blocks to supply some of the missing signals in the beginning. good luck~
Give a slow varying ramp input to your mdac block.. You must get a residue plot as shown in this figure.. This one is for one block.. You cascade many such blocks.. The frequencey of the residue(i mean the periodicity) increases with the
for a 1.5 bit per stage pipelined adc, due to digital correction,the comparator can tolerate offset voltage of +-vref/4,what i want to ask is that in the offset range of +-vref/4,if the settling accuracy of mdac is not enough,i.e. for 10 bit resolution and full range of 1V,the settling error is larger or smaller about 1mv,that is,for output (...)
i want the schematic of an mdac stage using opamp sharing technique used for pipelined adc. what are the difficulties one would experience in an opamp sharing architecture when compared to the conventional mdac type?
friends, i want the schematic of an mdac stage using opamp sharing technique used for pipelined adc. what are the difficulties one would experience in an opamp sharing architecture when compared to the conventional mdac types? thank you,