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The identical gain stages in DA, if I have 5 of them, can I say that it is a 5 stage DA?No one can understand what you want to mean. Describe correctly.
Hi, So with a quick opamp. I need to detect overcurrent and and turn off IGBTs An OPAMP is an amplifier, it has an analog output. To detect "= logic output" you should use a comparator. (Although OPAMP and comparator share the same schematic symbol, they are designed for different operating conditions. It has been discussed severa
Hi, I am trying to understand the connection between the two USB classes CDC and HID and four types of following data transfers. Control Transfer Isochronous Transfer Interrupt Transfer Bulk Transfer Is it possible to implement these transfer types in both CDC and HID USB class? Is it possible to achieve Full Speed (12 Mbps) in bo
I'm using a classic TIA configuration to measure leakage current through coax insulation in the 200nA range. The circuit works well using a V source and resistor to calibrate but when I connect the long, high capacitance cable the noise is terrible. Can I bandwidth limit the op amp to say 1-2Hz using a large capacitance across Rf (1 Megohm)
What do you mean you want to "capture a jitter"? Do you mean you want to measure jitter? Maybe you want to capture a glitch? Please elaborate
They don't use lockups in functional logic b/w asynchronous domains but synchronizers like 2-D flops (among other structures for multi-bit transfers). Phase difference b/w any two edges of async clocks is not guaranteed and so lockups are not exactly a reliable solution. Does this mean the 2 scan clocks are generated synchronously from the OCC to m
Are not gate level simulation always done on netlists? The post was raised for gate level simulation on one can understand what you mean. Express in detail with correct terminology. Do you mean Gate-Level-HDL which is synthesized from RTL-HDL ?
We have used fdtd configuration inputs: port1, port2 output: port3 RT 5880 I want to know if it's right or wrong: for the calculation of s21, the two ports port1 and port2 will be excited at the same time by two excitations and we calculate the fields? Ports are not excited simultaneously by definition of s-param
- LVS means Layout versus Schematic comparison - ERC means Electrical Rules' Check - DRC means layout Design Rules' Check These all are necessary checks with their own rules' sets. Depending on the PDK set-up, they can be called as separate checks, or all together (in series). - ARC, the Antenna Rules' Check actu
Hi, I am trying to design BJT circuit using TSMC 180nm BCD gen 2 process. It is my first BJT circuit. so i'm worried whether the fabricated circuit will work well as simulated or not. TSMC gives unit cells of BJT. I will place a thousand of BJT unit cell to drive large currents. Is it works well as simulated? Please tell your experience abo
Hello all, I am unable to simulate D-flipflop properly in AMS. The input that i am giving is itself shown incorrect on the wave form window. I was able to simulate simple gates but find ing problems with D flip flop. Attaching the code and waveform. module DFF_VERI(D,clk,Q); input D; // Data input input clk; // clock input output reg
I was watching this video from GreatScott And I was wondering about something that he said in the video at 4:43 (the link will take you to that time). He said something like this. Impedance of the primary is 1605 ohms, that gives the current I=143mA. In reality we get about 40mA current. "The reason is that ma
Assume three mobile phones, A, B and C. Their Distances from base station are different. Distance of A is small. Distance of B and C is large. Consider tx power control from base station. TX power for A is small. On the other hand, TX power for B and C is large. So A undergoes large two interferences.
Hello My company has developed a way of removing body and facial hair for cosmetic reasons. It involves high frequency flashing (~1KHz) of high intensity light into the skin. The skin is flashed with pulses of light, and each light pulse is further divided up into finer light pulses. Nobody else is doing it like this, and it works better. Th
You question isn't clear. What do you mean by input capture and output compare? If you already have an architecture diagram post it so we have an idea what you are trying to do. If you just mean a register and a compare then... -- register (for capturing) process (clk) begin if (capture_input = '1') then capture_reg <
This is related to parasitics extraction in spef files. All I know is that In IEEE standard spef files, there could be asymmetry between the coupled nets. Consider this case: D_NET foo *CONN .. .. *CAP 1 foo:1 bar:2 Here, there is coupled capacitor between foo and bar at nodes 1 and 2 respectively with val
I can understand AoA(Angle of Arrival) as Spatial Spectrum Estimation. However I can not explain AoD(Angle of Departure) well. How can I interpret AoD ?
What do you mean by “in Cadence” ? Do you visit Cadence office and are you there now ?
I assume you mean 30A->60mV not mA. Shunts convert current to voltage. Use a volt-meter to measure the shunt.
How the impurities are different from traps ? Also in acceptor impurity, can the electrons from the ionized boron acceptor level jump to Conduction Band at 300 K?