354 Threads found on edaboard.com: Mean Well
Is the attached mains waveform ever likely to occur? (i mean in the mains system and not due to any triac etc at the customer premises)
As you can see, it keeps going to zero for an interval, then suddenly coming back on at the mains peak.
As you can well imagine, this kind of waveform would be very bad for Single stage Power factor co
Power Electronics :: 03-01-2017 00:29 :: treez :: Replies: 0 :: Views: 319
The impedance matching of the IC with this matching network is great (measurement:s11<-30dB).
Now the strange thing: The sensitivity is better with a matching network, which is not very well matched (s11 ~ -7dB).
The difference is around you mean the followings ?
RF, Microwave, Antennas and Optics :: 02-15-2017 12:35 :: pancho_hideboo :: Replies: 3 :: Views: 433
What do you mean by "see the address of DDR memory"?
You write to a known location of the DDR3 using the MIG interface and then read back from the same address. If if get back the data you have written, your design is functioning.
Are you using a MIG with AXI interface? well then the AXI response channels (B*/R*) will also indicate if handsha
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-28-2016 12:28 :: dpaul :: Replies: 7 :: Views: 1337
And at receiver side I used simple 7805 regulator circuit for charging purpose.
What does that mean? We would at least expect rectifier and filter capacitor circuit.
You are talking about resonance, but there's no resonance capacitor at the transmitter side. And there should be a resonant receiver circuit as well.
Instead of g
Microcontrollers :: 12-13-2016 22:01 :: FvM :: Replies: 2 :: Views: 463
What is red sign in version limit column of vivado license manage(VLM) mean although Expiry date is not reached (see attachment).
I am asking because same reference design which was working 2 months before didn't work now. Although it has no error during bitstream generation as well as sdk programming.
This is the reference design:
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-28-2016 10:13 :: beginner_EDA :: Replies: 1 :: Views: 749
Phase huh? well you are sampling the RF signal at the LO rate, so the phase information is based on when the LO sine wave hits its peak...that is approximately when the sample happens. But since the output IF frequency is not zero...what exactly does "phase" mean to you? You can put in a constant RF, and constant LO, and you will get out a vary
RF, Microwave, Antennas and Optics :: 10-12-2016 15:50 :: biff44 :: Replies: 3 :: Views: 637
If by 'safe' you mean "will it blow up anything" then the answer is probably no.
The worst is that it may not work as well as you expect if the different antenna increases the SWR. The range will be reduced on transmit.
Depending on the country, GSM frequencies are generally in the ranges of 810MHz, 850MHz, 900MHz and 1800MHz whereas the WiFi frequ
RF, Microwave, Antennas and Optics :: 10-13-2016 21:57 :: Aussie Susan :: Replies: 3 :: Views: 683
Then the load should be connected after transistor, not before.
Top - I mean that schematics looks incorrect.
PCB Routing Schematic Layout software and Simulation :: 08-18-2016 11:02 :: Easyrider83 :: Replies: 4 :: Views: 488
it depends what the base type is. I assume it's ambiguous as it doesnt know if ( x ( 0 ) ' range => '0' ) is a bit_vector, std_logic_vector, signed or unsigned.
use a qualification to say which one you mean:
x <= x ( 1 to a - 1 ) & std_logic_vector'( x ( 0 ) ' range => '0' ) ;
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-28-2016 14:35 :: TrickyDicky :: Replies: 3 :: Views: 964
The problem is in line 24 of your code.
You got what I mean?
--> how can we help when you don't show us your code?
Or do expext someone writing the code for you?
Microcontrollers :: 08-15-2016 08:30 :: KlausST :: Replies: 2 :: Views: 365
What you mean by feeding line is PEC?
If you want to define the port then that face must not be PEC.
You can use tutorials about how to define PORTS in HFSS.
I tried to answer what i get from your post.
Explain further if you have issues
Electromagnetic Design and Simulation :: 07-04-2016 06:33 :: nomigoraya :: Replies: 3 :: Views: 597
the netlist work well on hspice but when simulating the same on tanner 13, i am getting two fatal errors. is there any mean to convert netlist syntax,
Software Problems, Hints and Reviews :: 05-12-2016 04:57 :: iti :: Replies: 0 :: Views: 443
well to be honest i reckon code to do class d amplifier is what you want, (you might get some off the diyaudio site) because that is the same sort of thing, yes, i believe at 500w and above smps's are pfc'd with active pfc so a pure sine wave is needed to be supplied to them....well.....pretty pure...i mean, the input LC filter of the pfc (...)
Power Electronics :: 04-29-2016 18:36 :: treez :: Replies: 4 :: Views: 773
You mean like one of these chips..
..what you are asking, the “silicon floor planning” of it, well, I always assumed that was secret info held in top security by those fab houses who know it
Power Electronics :: 04-26-2016 21:18 :: treez :: Replies: 5 :: Views: 678
The more immediate question is, "is the extracted value
wrong?". More likely to me is that the new art has some
error in it. Figuring that the foundry has pretty well
verified the extraction deck beforehand.
Properties don't mean a thing, by themselves. It's all
about the uses to which they are put.
If a library resistor of the same species ve
Analog Circuit Design :: 03-23-2016 18:47 :: dick_freebird :: Replies: 4 :: Views: 805
What do u mean by spi interface is fully static?
A well defined technical term. Fully static means, the communication can be paused for infinite time and restarted at any point of the protocol.
The 2 SPIs are separated so why they are affecting each other
Apparently they are not completely separated in your code
Microcontrollers :: 03-13-2016 13:09 :: FvM :: Replies: 3 :: Views: 458
Not clear what exactly do you mean by that, but as a general answer to this somewhat general question, the testbench/stimulus format entries depends either on the language or tool that you're using for that simulation, as well as the result would mainly depends on the technology of the manufacturer standard cells.
ASIC Design Methodologies and Tools (Digital) :: 01-30-2016 13:43 :: andre_teprom :: Replies: 5 :: Views: 651
well, depends on what you mean by a "board". If you have resonant elements like bandpass filters printed on the board, good luck with coating them! If you are just running very short traces of 50 ohm lines interconnecting chips, you might get away with it. And you COULD deliberately change the impedance of the lines to say 60 ohms, in the hope t
RF, Microwave, Antennas and Optics :: 01-12-2016 10:31 :: biff44 :: Replies: 2 :: Views: 1604
A nominal supply voltage of 19 V doesn't mean that the device actually needs 19V. I would check what's the minimal voltage for regular operation.
Hobby Circuits and Small Projects Problems :: 11-05-2015 12:37 :: FvM :: Replies: 7 :: Views: 1415
You mean the minimum mask-to-mask feature, the spacing of the soldermask pads? It should be at least 2 mils, possibly more depending on the PCB technology, otherwise there's a risk of small mask strips breaking off and lying around on the pads.
PCB Routing Schematic Layout software and Simulation :: 11-02-2015 14:06 :: FvM :: Replies: 15 :: Views: 1387