354 Threads found on edaboard.com: Mean Well
Is the attached mains waveform ever likely to occur? (i mean in the mains system and not due to any triac etc at the customer premises)
As you can see, it keeps going to zero for an interval, then suddenly coming back on at the mains peak.
As you can well imagine, this kind of waveform would be very bad for Single stage Power factor co
Power Electronics :: 03-01-2017 00:29 :: treez :: Replies: 0 :: Views: 298
The impedance matching of the IC with this matching network is great (measurement:s11<-30dB).
Now the strange thing: The sensitivity is better with a matching network, which is not very well matched (s11 ~ -7dB).
The difference is around you mean the followings ?
RF, Microwave, Antennas and Optics :: 02-15-2017 12:35 :: pancho_hideboo :: Replies: 3 :: Views: 400
What do you mean by "see the address of DDR memory"?
You write to a known location of the DDR3 using the MIG interface and then read back from the same address. If if get back the data you have written, your design is functioning.
Are you using a MIG with AXI interface? well then the AXI response channels (B*/R*) will also indicate if handsha
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-28-2016 12:28 :: dpaul :: Replies: 7 :: Views: 997
And at receiver side I used simple 7805 regulator circuit for charging purpose.
What does that mean? We would at least expect rectifier and filter capacitor circuit.
You are talking about resonance, but there's no resonance capacitor at the transmitter side. And there should be a resonant receiver circuit as well.
Instead of g
Microcontrollers :: 12-13-2016 22:01 :: FvM :: Replies: 2 :: Views: 440
What is red sign in version limit column of vivado license manage(VLM) mean although Expiry date is not reached (see attachment).
I am asking because same reference design which was working 2 months before didn't work now. Although it has no error during bitstream generation as well as sdk programming.
This is the reference design:
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-28-2016 10:13 :: beginner_EDA :: Replies: 1 :: Views: 678
Phase huh? well you are sampling the RF signal at the LO rate, so the phase information is based on when the LO sine wave hits its peak...that is approximately when the sample happens. But since the output IF frequency is not zero...what exactly does "phase" mean to you? You can put in a constant RF, and constant LO, and you will get out a vary
RF, Microwave, Antennas and Optics :: 10-12-2016 15:50 :: biff44 :: Replies: 3 :: Views: 582
If by 'safe' you mean "will it blow up anything" then the answer is probably no.
The worst is that it may not work as well as you expect if the different antenna increases the SWR. The range will be reduced on transmit.
Depending on the country, GSM frequencies are generally in the ranges of 810MHz, 850MHz, 900MHz and 1800MHz whereas the WiFi frequ
RF, Microwave, Antennas and Optics :: 10-13-2016 21:57 :: Aussie Susan :: Replies: 3 :: Views: 665
Then the load should be connected after transistor, not before.
Top - I mean that schematics looks incorrect.
PCB Routing Schematic Layout software and Simulation :: 08-18-2016 11:02 :: Easyrider83 :: Replies: 4 :: Views: 457
it depends what the base type is. I assume it's ambiguous as it doesnt know if ( x ( 0 ) ' range => '0' ) is a bit_vector, std_logic_vector, signed or unsigned.
use a qualification to say which one you mean:
x <= x ( 1 to a - 1 ) & std_logic_vector'( x ( 0 ) ' range => '0' ) ;
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-28-2016 14:35 :: TrickyDicky :: Replies: 3 :: Views: 852
The problem is in line 24 of your code.
You got what I mean?
--> how can we help when you don't show us your code?
Or do expext someone writing the code for you?
Microcontrollers :: 08-15-2016 08:30 :: KlausST :: Replies: 2 :: Views: 345
What you mean by feeding line is PEC?
If you want to define the port then that face must not be PEC.
You can use tutorials about how to define PORTS in HFSS.
I tried to answer what i get from your post.
Explain further if you have issues
Electromagnetic Design and Simulation :: 07-04-2016 06:33 :: nomigoraya :: Replies: 3 :: Views: 583
the netlist work well on hspice but when simulating the same on tanner 13, i am getting two fatal errors. is there any mean to convert netlist syntax,
Software Problems, Hints and Reviews :: 05-12-2016 04:57 :: iti :: Replies: 0 :: Views: 419
well to be honest i reckon code to do class d amplifier is what you want, (you might get some off the diyaudio site) because that is the same sort of thing, yes, i believe at 500w and above smps's are pfc'd with active pfc so a pure sine wave is needed to be supplied to them....well.....pretty pure...i mean, the input LC filter of the pfc (...)
Power Electronics :: 04-29-2016 18:36 :: treez :: Replies: 4 :: Views: 734
You mean like one of these chips..
..what you are asking, the “silicon floor planning” of it, well, I always assumed that was secret info held in top security by those fab houses who know it
Power Electronics :: 04-26-2016 21:18 :: treez :: Replies: 5 :: Views: 654
The more immediate question is, "is the extracted value
wrong?". More likely to me is that the new art has some
error in it. Figuring that the foundry has pretty well
verified the extraction deck beforehand.
Properties don't mean a thing, by themselves. It's all
about the uses to which they are put.
If a library resistor of the same species ve
Analog Circuit Design :: 03-23-2016 18:47 :: dick_freebird :: Replies: 4 :: Views: 755
What do u mean by spi interface is fully static?
A well defined technical term. Fully static means, the communication can be paused for infinite time and restarted at any point of the protocol.
The 2 SPIs are separated so why they are affecting each other
Apparently they are not completely separated in your code
Microcontrollers :: 03-13-2016 13:09 :: FvM :: Replies: 3 :: Views: 447
Not clear what exactly do you mean by that, but as a general answer to this somewhat general question, the testbench/stimulus format entries depends either on the language or tool that you're using for that simulation, as well as the result would mainly depends on the technology of the manufacturer standard cells.
ASIC Design Methodologies and Tools (Digital) :: 01-30-2016 13:43 :: andre_teprom :: Replies: 5 :: Views: 628
well, depends on what you mean by a "board". If you have resonant elements like bandpass filters printed on the board, good luck with coating them! If you are just running very short traces of 50 ohm lines interconnecting chips, you might get away with it. And you COULD deliberately change the impedance of the lines to say 60 ohms, in the hope t
RF, Microwave, Antennas and Optics :: 01-12-2016 10:31 :: biff44 :: Replies: 2 :: Views: 1402
A nominal supply voltage of 19 V doesn't mean that the device actually needs 19V. I would check what's the minimal voltage for regular operation.
Hobby Circuits and Small Projects Problems :: 11-05-2015 12:37 :: FvM :: Replies: 7 :: Views: 1291
You mean the minimum mask-to-mask feature, the spacing of the soldermask pads? It should be at least 2 mils, possibly more depending on the PCB technology, otherwise there's a risk of small mask strips breaking off and lying around on the pads.
PCB Routing Schematic Layout software and Simulation :: 11-02-2015 14:06 :: FvM :: Replies: 15 :: Views: 1341
In Full Bridge SMPS type converters, why do people use pulse transformers on the bottom FET drives as well as the hi side FET drives?
I mean, presumably its so that the propagation delay of the switching signal is equal for both top and bottom FETs, but isn?t this pointless? The 70ns or so delay is too short to be of any
Power Electronics :: 10-03-2015 20:59 :: treez :: Replies: 9 :: Views: 862
can anyone provide the links to download questasim for simulating s.v project.
I am assuming the by "s.v" you mean SystemVerilog. well if this is so, then let me also warn you that Questasim does NOT support all SV constructs. This is from my experience in 2014 when I was trying to compile & simulate a given uP core mo
Software Links :: 08-07-2015 15:09 :: dpaul :: Replies: 3 :: Views: 71
This array would be able to hold a 4x4 matrix of bytes
Didn't you mean 8X4 ?
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-17-2015 10:45 :: shaiko :: Replies: 4 :: Views: 1401
Are you sure that you don't mean backdrilled via, a commonly used technique in high speed PCB design.
Elementary Electronic Questions :: 06-05-2015 15:19 :: FvM :: Replies: 3 :: Views: 604
A "graph" is visual representation of data. When you say you are trying to "import my graphs" do you really mean you are trying to import data from an NI system into matlab? What is the format of that data? Is it compatible with Matlab? Is it ASCII text?
Software Problems, Hints and Reviews :: 03-26-2015 14:34 :: barry :: Replies: 6 :: Views: 1048
Can any one help me in calculating mean square value of noise voltage in passive circuits (containing R L C only)..Suppose the output of interest is voltage across any one of the capacitor (there may be other capacitors as well)
How can we apply the equipartition law for thermal noise here?
Analog Circuit Design :: 02-27-2015 17:30 :: jiripolivka :: Replies: 4 :: Views: 548
Thank you.For comparator design which type is better i mean nmos_1v or nmos_hvt(for low power,high speed apps).
Analog Circuit Design :: 02-19-2015 08:37 :: kvk1806 :: Replies: 2 :: Views: 892
well negative IR drop would be mean the circuit has inductive properties... it is usually seen in package and power grid simulations. this package inductance usually causes the power bumps which cause vdd surge in the chip power network. this is not acceptable because it causes a ringing effect on the power network. As the voltage goes more than V
ASIC Design Methodologies and Tools (Digital) :: 02-04-2015 19:55 :: artmalik :: Replies: 1 :: Views: 962
I am trying to understand the VHDL code of a third-party to control a Micron DDR2 MT47H64M8 – 16 Meg. And after reading in the Datasheet, I can´t understand very well what is the meaning of Write Burst and Read Burst. What does it mean when it says: "The burst length determines the maximum number of colum
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-19-2014 00:38 :: ads-ee :: Replies: 2 :: Views: 1194
I have a circuit and I want to connect it to an touch LCD and I want to connect it to a potentiometer or 6 resistors . I mean i want to use 1 mount of resistor at the time by pressing touch LCD
Does the "circuit" that you are talking about include a Microcontroller as well?Are you making a resistive type touch screen LCD?Please exp
Microcontrollers :: 11-12-2014 14:58 :: udayan92 :: Replies: 3 :: Views: 643
Of course it does: if there is no feedback, then you don't have much to control.
Example: input signal -> amp -> output signal. (well, there might be a closed loop in
the amp, but this is another story).
If you check for stability, it means that you have some kind of loop, the most usual
being input -> subtractor -> amp -> output and feedba
Analog Circuit Design :: 11-05-2014 01:10 :: doraemon :: Replies: 4 :: Views: 853
well, I am confused, too. What do you mean "what is the relation"?
x is unknown; y is unknown==> relation is unknown.
The phase difference between the two waves is 2x-y. Is that significant?
Actually, you seem to be missing something. If x and y are constants, your two signals are also constants. Is there supposed to be a "t" in there
Mathematics and Physics :: 10-22-2014 19:41 :: barry :: Replies: 5 :: Views: 1384
I came across a statement "analog front ends can be protected against leakage currents by incisions in board layout".
What does incisions in the board layout mean?
How is it obtained?
PCB Routing Schematic Layout software and Simulation :: 09-20-2014 14:06 :: at89atbits :: Replies: 6 :: Views: 570
what would be the use of a DC converter if it could not run without load?
The question should be passed to meanwell. I was just referring to the datasheet.
Service Manuals, Requests, Repair Tips :: 07-22-2014 15:33 :: FvM :: Replies: 4 :: Views: 752
well done, its always good to see your lcd come alive.
Not sure what you mean by adding a lookup table, to the lcd routine ?
You can advance your existing routine by introducing 32 user registers to hold the data to be displayed, see the attached sample coded.
With this its easy to call predefined messages and update the registers /di
Microcontrollers :: 07-12-2014 16:30 :: wp100 :: Replies: 13 :: Views: 2440
Two reasons. Without continuity, the design rules would probably mean you would need to space things further apart. Also, the wells need to be tied to VDD/VSS. If they're continuous, you need less well ties.
ASIC Design Methodologies and Tools (Digital) :: 06-12-2014 11:55 :: jbeniston :: Replies: 1 :: Views: 1339
do you mean like having a 3-phase controlled rectifier and you change the firing angle to acheive the variable DC voltage you want?
well, at least i said something :)
Power Electronics :: 05-31-2014 22:29 :: Mr.Cool :: Replies: 5 :: Views: 1047
i am not sure i understand well. Do you mean that you want the tool to use more realistic switching activity - in which case you should read an activity file (.tcf, .vcd, .saif)
Or is your point to have it propagate from top level once you set some values there.
In RTL Compiler there is quite some flexibility on this aspect. you should check some
ASIC Design Methodologies and Tools (Digital) :: 05-13-2014 05:16 :: englishdogg :: Replies: 2 :: Views: 1088
i need information about frequency trimming, i want to know what is frequency trimming and information about it's basics, please help me and if you know any reference in this subject introduce to me, thanks
ASIC Design Methodologies and Tools (Digital) :: 03-30-2014 07:54 :: mostafah67 :: Replies: 5 :: Views: 1095
for the training mode, my model works well. When transfer to the Direct Decision Mode, I am confused about how to realize the Decision Device , specifically , I do not know how to choose the right reference value for decision. The mean of the equalized signal? I have tried but not work well.101283 Channel is based on the sin
Digital Signal Processing :: 01-20-2014 14:59 :: suken :: Replies: 0 :: Views: 666
I would need to built my own oscillator inside the circuit since no function generator is available in this frequency.
You mean, not available in your lab. But it's a standard RF generator.
40 Vpp correspondends to 4W into 50 ohm, well in the range of medium power wideband amplifiers.
A point that should be clarified first is
Analog Circuit Design :: 11-17-2013 19:55 :: FvM :: Replies: 9 :: Views: 1031
What do you mean by "Matched hfe to ~7"
Show DIY :: 11-03-2013 12:23 :: FvM :: Replies: 35 :: Views: 9326
Out of interest, China now does much of the Electronics for the West now, certainly the more simple PCBs.
Does any reader know what are the PCB Layout Software packages commonly used in China?
I mean, the Chinese are doing Electronics very well, everybody seems to be going there to get their electronics done, they must be doing somethi
PCB Routing Schematic Layout software and Simulation :: 10-30-2013 12:11 :: treez :: Replies: 1 :: Views: 769
Can someone tell me what the different types of layers are for, I mean some of them are pretty obvious like Top Silk, but, Top Assembly, and Top Placement... what's the difference. I'm a little confused. Your help is appreciated.
PCB Routing Schematic Layout software and Simulation :: 10-27-2013 02:26 :: DanHHunter :: Replies: 2 :: Views: 1115
well , its hard to get static IP. I mean when you are using gprs connection is dynamic always.
My suggestion is, in wt ever project you are doing
1)First dont ON the gprs.
2)wait for the user form other side to send his IP via a text msg.
3)then by using his IP as server address, now you can ON you GPRS and start communication with that IP( i.e so
Microcontrollers :: 10-24-2013 17:05 :: boddusaipavan :: Replies: 1 :: Views: 1257
Do you mean Ethernet to serial device? All major manufacturers have controllers that can do the job, e.g. Microchip PIC18F97J60, ARM based processors from ST and others. Most vendors have application notes, software IP stacks, development boards to get started as well. You could even buy off-the-shelf Ethernet to serial modules
Network :: 10-24-2013 05:24 :: hemanteda :: Replies: 1 :: Views: 909
I have mean well usp-350-3.3 power supply. This supply has 3.3V/70A (with air cooling) output but I need 1.2 V/50A output.
This supply has regulated output voltage in range 2.7 - 3.6 V using potentiometer.
My question is: If I change potentiometer and voltage to 1.2V power supply will be working good ? What about the current?
Power Electronics :: 10-17-2013 10:44 :: certino :: Replies: 0 :: Views: 627
... I need an ATX power source ...
what exactly do you mean by this ? Does this mean that you need to convert a 19-60vDC to multiple outputs @ 3.3v, 5v, +12v, -12v ?
Analog Circuit Design :: 10-11-2013 04:23 :: kripacharya :: Replies: 3 :: Views: 660
You mean you want to write a code for MSP430? Are you newbie in this field or you have some experience. Instead of writing a code, try to spend some time on the reference code which is easily available on the TI site. Otherwise you could get the reference code wit h your senior. Every one need a reference code. Without a reference its not easy for
Microcontrollers :: 09-16-2013 12:27 :: shaswat :: Replies: 4 :: Views: 625
Have you tried a small capacitor across your feedback resistor? Have you tried changing your resistor values?
Not sure what you mean by "200V p-p input", but it sure sounds scary. Do you have a schematic?
Analog Circuit Design :: 10-02-2013 19:46 :: barry :: Replies: 11 :: Views: 2188