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55 Threads found on edaboard.com: Memory Chip Design
It depends on RdsOn or Rce of memory cell and source + load capacitance such that t=RdsOn(Coss+Cload) my speculation....1ns is possible with 120nm litho
132539 Is this a good design? A CPU + GPU PCIe card with Intel Xeon e3 v4 processor with super high speed memory and Tesla type GPU in the same chip so it has less bottlenecks with PLX chip.
In my design I am having ADC, DAC and memory blocks. Since the chip deals with both analog and digital signals, what care should I take while placing these macros and in subsequent stages of the PnR flow?
I'm a hobbiest trying to design a LIDAR system. The controlling computer may be a Pi Zero @ 1 GHz. It will fire a 100 nanosecond pulse, wait 100 ns. and then use a fast A/D to digitize the return every 100 nanoseconds for 50 samples total. The samples will be stored in a fast FIFO memory chip. Then the computer will wait 100 microseconds for (...)
100 cores of what? Nios relies on the Avalon Bus - usually with the Nios acting as the master and other units connected via a memory mapped avalon interface. This way you can have any existing IP or any other IP you chose to design yourself (as avalon is a straight forward interface, very similar to AXI). NoC is usually a term used for Asic, not
Here has 2 memory device A and B: The active current of A is 10 mA, B is 20 mA; and leakage current of A is 20 uA, B is 10 uA. For a hand on SOC design, like cellphone processor chip, which memory device is better choice? A or B? Please help me.
Hi Is there any formula between flash memory capacity Vs die space occupied? Thanks
compressed scan technique is to reduce the amount of data needed to check the design, due to limitation of tester memory size.
HI all, I want to gate the Address, Data bus of the memory when not selected from controlled. what is the best possible ways to do it without adding more area on the address and data bus?
A microprocessor is the core computing part with the ALU, instruction decode and execution unit(incl. microcode) - but without memory(data/program) and pheripheral I/O units. A microcomputer has all component on a single chip. Microcomputer targetted for controller(or embedded) application are called microcontroller. Enjoy your design work!
I want to design a simple memory in vhdl language using registers. I am using Xilinx kit Spartan 3 chip
Dear, I don't see any memory with JTAG interface. Why memories generally do not have JTAG though they are coming in BGA packages? Please respond. Regards, Thulasi
Can you find information of FPGA chip on memory maximum limit ? Simple calculation form don't have memory management for safe work .
I need to implement an on chip multi-port memory in a design Is there a multi-port memory compiler than can generate a cache with more than 2 ports ?, or do i need to code it myself ?
Read the specs for the chip. See how big the memory blocks are. But, if you have to ask how "big" you can have an array, I suspect you need to learn more about digital design. And if you need to ask, your array is probably too big.
Find the books at for VHDL imprementation or workshop on chip design. Own, I think the matrix form instead memory if you are mathematician or can be use the input vector files.
Hi I'm designing a board with a CPU that has no DM (data mask) pins on it's DDR3 memory interface. Where should I connect the DM pins on the DDR3 memory chips? GND, or VCC, or what?
Hi What is ur memory requirement?Now days single chips are available up to 8Gb..Attached data sheet is a single chip which support 4Gb memory..
Well, the on-chip RAM is synchronous and so is the circuitry you will design to access it. Therefore your main concern is knowing in which clock cycle your output data is valid and using it at that time. When the output data is available varies based on whether or not you register the outputs and what memory implementation you chose from (...)
Functional mode is the one in which the chip normally operates, or is required to operate i nits end application. rambist is built in self test for memories, to make sure memory is working properly and doesn't have junk data in the output. Scan modes are for testing the flops in the design through scan chains. I guess capture and shift are (...)
it is used for communication within a soc for different components like processor, memory, coprocessor, etc. Please look at the attachments in this thread:
you noted, you have simulated the mbist, so you know waht it is doing? if I write a ATE test, I expect during my simulation to see from outside the DUT, the result of my bist for example, no? I means I control the start of the bistt, I know when it is finished,and I know when it pass or faild (I forced some error in memory).
VLSI memory chip design (Springer Series in Advanced Microelectronics) (v. 5) Kiyoo Itoh (Author) Hemming code is important part of memory design Hamming code - Wikipedia, the free encyclopedia
Get the knowledge of cheap accessable communication IC's, then choose a brain chip and memory topologies. reconsider and repeat, then look how far You are from the BeagleBoards of TI chips and look at these, or cheat and start there. Choose an os and write some emulation test codes for the Beagle. Many of the modules from the tablet is ready (...)
did you mean, read two memories, make a comparaison and save the result in a third memory when different to zero? why system verilog? It is not usable to design a chip, but for test/verification.
Hello, I am developing a design for a new microarchitecture as part of a research project. I am using VHDL to create a model of this architecture . Our goal is to estimate the performance of this architecture from simulation results, and not necessarily to actually get it running in a chip. Eventually, we will protype it on an FPGA if our simul
I'm starting a new design that requires the quick transfer of a few megabytes of data between a FPGA and a microcontroller. The FPGA is the Altium Cyclone IV processor (EP4CE15F17I8L), and the microcontroller is the AT91SAM9RL64-CU microcontroller, which is an ARM9 chip with external EBI bus. Attached to the FPGA is a SDR SDRAM from Micron (M
Hello, In a design for a class (a bad design IMHO, but I have to deal with it...), a chip access an external asynchronous memory. Therefore, there is a path from the transition of addr rd/wr signals to the output pads to the async memory to the input_pad to the input registers in my (...)
Hi , what's "factor for de-skewing of memory" in p&r ?????? thanks
Hallo, gerade lese ich ein Paper: "an SDRAM-Aware Router for Networks-On-chip". Der Begriff "aware" bedeutet gewahr, bewusstwahrnehmen aber was ist der funktionale Unterscheid zwischen einem Speicher (memory) und einem memory-aware? Auf eure Antwort wuerde ich mich freuen. Sara
Hi, I met a question in my design of DFT for a SOC chip. In this SOC, there are PLL and many memory modules. I want to bypass the memory when testing, so I change the RTL code to add a bypass function to them, but I find this method does not work. In RTL code, I added a mux which is controlled by the test_en signal of the (...)
I have built an ADC/DAC card for ISA BUS and I'm trying to rebuild it for PCI BUS using PCI9052 chip from PLX.I need information on pins and design considerations. Is it enough to connect the pins or I need to input some information into its memory? Where can I find some bridge examples? Any information or comments is appreciated. (...)
Transactions to the external memory are the largest contributors (memory IO and internal bus dynamic power) to the system power consumption. Reducing external memory transactions – by improving cache size, scratchpad and on-chip SRAM. In embedded system design, the designer has to (...)
hi,everyone i simulate my design with an off-chip memory with these steps below: 1.if my memory is defined as following: module memory(...); ... reg mem ; ... 2.then i initialize it in my testbench: $readmemh("mem0.in", memory0.mem); (...)
I think the size you wanted is not very big, and the frequency is not very fast. choice is two: 1. you can implement inside the chip, but some cost on tester. 2. If you want a external memory employee, an exchange interface needed; and the memory chip timing is not common value, you must confirm the margin.
I am planning to design a mobile platform based on the Xilinx FPGA chip. Now the Virtex5 chip is so powerful: several PPC, network interface, memory controller and so on. For development, usually I bought the boards from the FPGA board providers. However, the board is always not perfect for the design. I (...)
some kind of shared-memory, connected with on-chip bus is common method.
use strong computer, and lot of memory. use linux not windows.
PLS HELP ME TO design CIRCUIT WITH DS89C320 ,.MICROCONTROLLER. HOW TO INTERFACE memory chipS.GIVE SCHEMATIC. have you read the datasheet? what type of memory would you like to interface? IS TYPICAL 8051 CIRCUITS COMPITABLE WITH THIS chip. yes most ci
Hi, I'm looking for some ideas to make an IDE to NAND or NOR flash memory interface. Have you ever heard something about this (ip, project, chip...) ? Thanks. Franck.
Sorry I dont think so Pepole approach memory vendors for MBIST etc
Do you have any idea about your design? 1. How big is the logic? 2. How much on-chip memory is required? 3. Do you need off-chip memory? What's the type? SRAM/SDRAM/DDR/DDR2/RLDRAM.. 4. How many pins are needed? 5. What's the IO standard?
Hi all, Normally, the phase margin is larger than 45 degree. But I heart that the PM of the voltage regulator in the nonvolatile memory can less than 45 degree from my leader. I don't know it's true. If you are the nonvolatile memory designer ,Can you give me the answer ?
Why memory Layouts designed primarily from the bottom up, instead of from top down, like other IC's?
hi u would need a compiler and an adapter that suits ur flash chip. u can order or copy a compiler from Kiel.com. they provide a free demo version, and works fine if ur code is less than 2K. if its more u would have to purchase. u write ur code in C or Assembly , compile it , and burn it in ur chip by placing ur chip in ur adapter and (...)
the code of cpu core is stored at DRAM. but as we know, DRAM has soft error(SE). When SE occured, the chip will die. So We can use ECC to correct 1 bit soft error of DRAM. my question is : Among SDR, DDR, DDR2, which one is more stable for code storage according to your SOC design experience.
have a look @ search forum 4 many low power docs some key tips are reduce clock and signal toggling. multi vt design. reduce memory,registers in design
Dear ALL, I am a newbie in this field (flash memory cell). This is the first time I get involve in digital staff. So, can anyone suggest some reading material for me (memory cell and digital basic)? thanks tok
soc (system on chip) an FPGA does not normally have ADC or DAC so you might need this if you are dealing with voice. IR-drop either my memory is failing or something because I don't know what IR is. Voice cross talk. Do you mean cross talk between channels? you won't have that problem on a digital design, Perhaps you meant to post in a (...)
I've got Orcad 10. I'd like to take some of the provided design files offered by micron and the other chip companies and have a PCB made for some testing. I'd also like to be able to tweak a few things as well. From what I can tell, they offer for download the following types of files: From JEDEC and the various companies: Gerber