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6 Threads found on edaboard.com: Memory Floorplan
Hi, I have a doubt regarding power structure for memory macro. Using memory compiler software, there is a space to specify the ring width for the memory macro block power ring. What should be the value for this ring width? Lets say we specify the value to 10 um. Now when we floorplan the design including this (...)
Hi all, Right now i'm doing floorplanning.. Is it possible to rotate macro - 90 degree? How to conform this with LEF.? regards. Nantha
Hello, I am using blast fusion and am facing this problem. there is a memory macro for which i have read the best case and worst case lib files and also the lef file during library preparation. But after floorplan and power ring creation around the macros, the pins of this particular macro are not routed to the power ring/mesh after i run run ro
hi, what's the reason for timing violation? and I think before post-clock we should focuse only on setup fixing. and where is you violation path located ? memory or hare macro ? if so, adjust your floorplan. and if you vio path located in standard cells , just check the topo of routing and check if it's reasonable.
Hi hossam Alzomor whether it is related to floorplan Issue? before posting reply u must check the question. Hi urslen 1.Macro r power hungry part of ur chip . and power routing is major problem for Hard macros like memory(RAM). 2. U must place blocks according to routablity and optimaztion /SDC constraint ISSUES
I have a chip require to place the 12 memory macro, one inisist place all of the memeory together and only the routing channel is reserved between the memory. But I think that the more space should be given to place some stdcells for meet the timing constraint. if only the routing channel is reserved, maybe the very long wire is required to stride