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388 Threads found on edaboard.com: Microblaze
i want to add a sequential D flip flop as a custom ip in a microblaze project in edk and run it using SDK , but i am not getting the required output , the main problem is to how to connect clock to the clock signal in my ip . can anyone please help thanks in advance
Hi bro. I have 2 questions, please answer me. 1-Why sometime for programming of microblaze in xilinx fpga use while(1) loop and sometimes dont? see below code for example... I want to generate a PWM signal using the Timer/Counter IP Core. Nothing shows up. What I did: Added the core, connected the PWM0 port of the core to an ex
Hi, I am using AXI GPIO IP core in combination with microblaze that write/read correct data from/to VHDL top entity. I wan to read data in microblaze from HDL top entity and do some command operation in microblaze. But the problem is whatever I r
Did you try to find it out by doing some search? The 3rd line of my search brings comes up uBlaze FAQ: Your Q is answered there in - How many microblaze processors can run on a single FPGA device? Regarding "independent and mutually exclusive" I think diggin
I am new to fpga design and have been tasked with a very complex artix based microblaze design at my company. :roll: I would appreciate any comments on wether this is suitable for my microblaze Artix based design or wether there should be any extra stages added? You need to write firmware for the u
Hello, for one project I need to use a L2 cache that offers more flexibility in terms of associativity than the IP core proposed by Xilinx (the associativity of System Cache is limited to 4 sets, I would like to use 16 sets or eventually 8). Can anybody give me a hint about a VHDL implementation of such a module that I can use for a microblaze proc
Hello, for one project I need to use a L2 cache that offers more flexibility in terms of associativity than the IP core proposed by Xilinx (the associativity of System Cache is limited to 4 sets, I would like to use 16 sets or eventually 8). Can anybody give me a hint about a VHDL implementation of such a module that I can use for a microblaze proc
Distinguishing the slaves is the mission from ID part from BUS protocol. It is not function/feature of microblaze.
hi I want to measure the maximum speed of read/write of my memory. I have a microblaze processor and a sdram in my design. I'm going to add a dma in order to write to memory. do you have any better idea? I can't find any good source or example for dma. could you please tell me, what should I do?? Thanks.
Hi, I have been create a simple microblaze project with only a 32 bit gpio prepheral. and when I start the sdk, using export w/o bit stream , and creat a new application project, this error occured when trying to build it : make all 'Building file: ../src/main.cc' 'Invoking: microblaze g++ compiler' mb-g++ -Wall -O0 -g3 -c -fmessage-le
But what I wonder here is about stand-alone ModelSim run, and we need to associate the software to microblaze. Can we do that ? In my opinion "associate the software to microblaze" is the work for Vivado, independent of the simulator s/w option. Just try it out. Please inform me if you succeed....this would be some handy info! [QUOT
Hi, I am using kintex kc705 FPGA board and VIVADO for following project: and it uses microblaze processor for software part. There is another project which is built over above project by adding additional compression(JPEG 2000) feature to it.
Hey guys I want to do a simple project with microblaze soft core in vivado. here is my design: 130163 and I have created a simple application project in sdk. here is my code: #include #include "platform.h" void print(char *str); int main() { init_platform(); while(1) print("Hello
If you are new to this type of work, use the Vivado block automation feature for the microblaze. Add the uB and then add the AXI DMA IP core and then run block automation. Pg23, to get started with block automation...........
I am looking to design a axi system with the IP's on a VC707 board in vivado. the IPs are 1. Mblaze 2. central DMA 3. block memory generator here i want to make Mblaze and central DMA as masters and rest of the things are slaves. In detail, central DMA should be a slave to Mblaze in one side and Mblaze should be a slave to central DMA on other
Hi, I would like to use the microblaze performance monitoring engine to collect some information on my application code running on the processor itself. I would need these information at application level. Xilinx proposes to collect low-level information by using XSDK "performance view": that is very clear, and it works good, but this type of so
Hello All, I am trying to synthesize and implement a soft microblaze core to know the approximate resource utilization on my Zynq FPGA. I am following the document and video from xilinx mentioned in the link below.
Hi to all. I have created a spi module with 8 bit width data. Now I WANT TO change it to a 16-bit one. To do this,I have change its property in XPS and now I should change the codes. I use this function to transfer data. Xspi_Transfer (&mySPI,data,NULL,1) The spi definition is now 16 bit but the function still in 8 bit mode. What should I
Hello all, I have had an about complex project using microblaze and so, Implemented in a v6-130t and ٍnow the employer asked me to displace it to v6-240t. what I have done to do this migration is regenerateing all the componnets such as IPs for new device. the problem is that in new project I can not program the fpga and debug the MBLAZE c
Hi, I have a complete Xilinx microblaze desing that is working on a specific FPGA. I got the design and want to use it on another FPGA that I have. How can I do that?