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Hi, I am wondering how to calibrate the acceleration sensors. The sensors I am working with are very similar to what we have on fpga development boards. I have readout electronics for sensors with can measure from 10 g to 100 g. I am not sure if get the accurate reading. I am wondering if there is available calibrated vibrating surface on which
Using Quartus 12, I would like to know why wait until ((clk'event and clk ='1') or (clk'event and clk ='0')); won't synthesize to a double edge (raise and fall) flip flop? I get this error Error (10628): VHDL error at test3.vhd(9): can't implement register for two clock edges combined with a binary operator Error (10658):
Besides spectrum analysers and oscilloscopes what other equipment is needed to be learned to perform testing Analog ICs and blocks? And who defines the standards for such characterization tests? IEEE? (I would like to hear especially from who has been in such a lab)
Hi, I planning to use common chokes on power distribution board to isolate modules's power. However, there are signal lines(UART and I2C) between modules. So there are two common chokes on the return path for I2C and UART signals and this anoys me so much. Common chokes are PL8205NL from PULSER. They have 768uH inductance. Max I2C speed is 400kHz
Hello, I am a beginner in fpga development. I would like to design applications in Financial Technology, Quantitative Risk Management/Simulation, High Frequency / Low Latency Algorithmic Trading, AI / Machine Learning and Digital Signal Processing. I am planning to buy the Nexys video Artix-7 to start developing the core fpga design skills an
Is there any essential diferrence as far as training time is concerned between a CNN running on a fpga and the same CNN accelerating on Google Coral Dev board? What I mean, is this: can I achieve faster training by using Google Coral Dev board instead of a fpga?
I recently installed quartus 17.0 lite version and wanted to target device 10M08SC324UBGA. To my surprise, software only supports dual supply version for this package. I could not find any info in the site or any forums. I thought all devices/packages were supported. any advice?
Is there any ability to switch between bitstreams in Single fpga? can i store these bitstrems on fpga's memory and then switch between them?
I want to accelerate CIFAR-10 dataset on a Virtex 5 fpga. I think I have built correctly the CNN on VHDL. My question is how I load the dataset on the fpga? Or should I send the images through another device/laptop on the fpga? I thought also of using SPI/I2C/UART/Ethernet but seems this makes a bottleneck? Right? Also, could it be better to (...)
Hello, I need guidance on using SFP port on ML605. I am unclear which IP core to use with it. There are a number of 1G and 10G cores available which confuses me. There are cores which state that they are MAC controllers, while some say they implement the PCS/PMA . which one do i exactly need?
Hello, I have an fpga clock coming into my design. I want to simply send this clock using another pin. From working with Xilinx - I learned that the recommended practice is to use an Output DDR Flip Flop for that purpose - as described in this link :
Hi, I want to write a c code for square wave converter for some calculation purposes, Actually have to do some process [ converting an analogue signal to a square wave . I don't have any idea about this logic in c language . Pls anyone suggest me the logic or code for square wave converter in C . [currently working with
Hii All , Currently i'm working with fpga. For that i need to convert analog signal into square wave for calculation Q is how to write a code for square wave converter in C programming. or what is the logic for that!! Pls suggest me c code for square wave converter. Thanks.
Hi All! I am very new to image processing. I am doing an online class in fpga open online course about self-driving cars. I facing with practice problems about lane detection using image processing, which is very stranger to me. Before I advance to the software part, I really want to solve edge detection using Sober Filter on Slopes and Diagonal
Benefits of using virtual clocks in SDR interfaces Suppose I have a simple SDR source synchronous interface sending data + clock to my fpga. The timing relationship between the data and clock are known - so I can proceed with constraining the input pins of my fpga with reference to that real clock. However, many examples recommend constraini
HI! My Nme is Riccardo i'm passionate for computer in general and electronic in general. My question is how do they detect the design of the DIE chip on a processor like Intel or new generation AMD and their files inside the chip such as e.g. RTL files etc ...?. With fpga hardware you can discover the architecture of the chip. I would like to
Hello, Is there any tool that can transform python code for Machine Learning into VHDL (preferably), so that can be uploaded to a Xilinx Spartan 3E fpga?
Hi guys, I'm just curious and not able to found the answer in the internet, how to calculate the delay using clock cycles. I have read that the equation is : Clock cycles =(time delay) *(clock frequency/4). how did it come to that equation (divide by 4). Thanks
Greetings ... comment that I am with a small project in ISE 14.5, I have managed to synthesize but I am having compatibility problems with the ipcore fifo_generator 9.3 when implementing and I am having one of the errors. ERROR:NgdBuild:604 - logical block 'u_client.U_client_ff' with type 'g1_ipcat_wbus_client_fifo' could not be r
I have a code and testbench for 128 x 32 single port RAM VHDL code, but the wave that I get is not correct. I am using a protected testbench created by my instructor. How should I change the code, I am on the learning process about RAM/ROM memories, so if you know something that I have to put in my code, please comment. Thanks LIBRARY ieee