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99 Threads found on Mixed Signal Simulation And
According to datasheet specifications, a 5V supplied cd40xx can reliably drive one LS input. I won't expect to get meaningful fan-out/fan-in simulation from Proteus. Like other SPICE based simulators, it uses a mixed-signal mode and doesn't fully model the analog properties of digital gates. There's also a large gap (...)
Hi, I'm new with AMS designer. I've few basic questions: 1. Could anyone please explain me the differences between co-simulation and AMSDesigner-with ultrasim simulation (AMS-Ultra)? 2. Does ultrasim support simulating RTL verilog codes? 3. How the mixed signal circuit gets simulated with AMS (...)
Dear All, I have need your help. I have a circuit with an analog part and a digital part. Now I am able to simulate in Analog-mixed signal Mode in virtuoso, in which the analog part as transistor level, while digital part as a functional view. I'm using only the virtuoso environment. My intent is to make the PVT (...)
Hello, I am using AMS to try mixed signal simulation with two inverters: one is in analog with nmos/pmos, the other is in verilog with "assign out =~in;", and the analog inverter will drive the digital one. The plot is not very precise as expected that the digital output didn't rise or fall corresponding to the vthi/ (...)
Yes - CustomSim will do mixed signal simulation. You'll need a VCS license for the HDL simulation part.
Analog, Digital or mixed-signal - which type of ckt simulation & design are you targeting? Depending on this your tools will vary.
hi, I am new user of cadence incisive unified simulator. I want to run a mixed signal simulation. I am able to run a mixed signal simulation of a design consisting of a verilog module and an analog schematic module, when using cells only from analogLib in the schematic. The (...)
I use ngspice because it contains analog, digital and mixed signal simulation. You can use kicad to generate netlists too.
Hi, I am trying to use SpectreVerilog simulator for mixed-signal simulation. I found a notes here I had a problem at the step of "Change Default IE Library Name to "UCD_Analog_Parts," or what ever your analog library is called, and press ok." Afte
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Hi, I'm trying to verify a mixed signal design that characterizes a load than applies voltage to that load. To characterize the load the circuit applies voltage to it than measures it's current. and in the second phase forces current through it and measures it's voltage. after taking into account these parameters voltage (...)
Not exactly the Cadence-specific answer you are looking for, but you can simulate these types of mixed-signal circuits quite well in CPPSIM and ViaDesigner.
ViaDesigner includes: Schematic capture, SPICE modeling, VHDL entry, Verilog entry, VHDL-AMS (analog & mixed-signal) modeling and all of these design entry methods can be combined in a unified simulation environment. Not free but on $169 for a 1-year license. Free 30-day trial available at
ViaDesigner is a mixed-signal design & simulation environment for Windows PCs. You can download a copy at
ViaDesigner is a high-level mixed-signal design and simulation environment. It also has a bunch of design wizards for useful functions like: ADCs, DACs, filters, etc.
ViaDesigner is not quite free - a one year license is $169. ViaDesigner is a mixed-signal design and simulation environment. It combines: schematics, SPICE modeling, VHDL, Verilog and VHDL-AMS into a unified simulator. You can download a trial version of ViaDesigner from
ViaDesigner is a VHDL-AMS based mixed-signal simulator. ViaDesigner contains Filter Design Wizards that generate readable VHDL-AMS. You can use these filter models as a starting point for your high-pass and low-pass designs. You can design and simulation continuous time and switched (...)
ViaDesigner is a mixed-signal design and simulation environment that combines schematics, SPICE, VHDL, Verilog & VHDL-AMS models into a unified simulation environment. There is a 30-day trial and although not free a one year license is $169. You can download at
Hi All, Is anyone know any reference design of AMS with Assertion Based simulation (ABV) environment. The assertions can be in SV or in PSL. Thanks in Advance
Does anyone use VCS-MX and HSPICE/finesim/finesimPro to do mixed-signal simulation? What is the methodology/flow? Appreciated if you can provide sample scripts. Michael