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19 Threads found on Modelsim Saif
Hallo, I would like to improve the power estimation by using switching activity. I use modelsim and design compiler and my question is: How can I dump all the signals in the saif file by using modelsim? Because my problem is, I can't see all the signals in my saif file,I see just part of them and the other part is (...)
Hi All, while doing power estimation after synthesis. i am getting not-annotated nets. How can we exactly map the names? How to solve this annotation problem? The saif file is generated using modelsim and synthesis file from design compiler. Please help. Regards
Hi, Check out the following link for performing Power simulation with Synopsys Power compiler saif files and modelsim.
hi. i want to find the dynamic power of a stage of my pipeline. i synthesized the decode stage of pipeline seperately and i maked the saif file by using rtl2saif command in design compiler. i used the saif file in modelsim. i got the activity of this stage by simulating some test program. then i used the (...)
modelsim create a VCD and from this one you create a saif, vcd2saif binary.
Salaam, You can do it using synopsis tools by means of saif or VCD file. To do so, you should run an application on this VHDL code when it is running on modelsim and dump switching activity and signal probabilities in a VCD or saif file. VCD file is rather easy but not applicable to large designs. How large is your code? Is it a processor?
Hello, I have made my system needed memory in memory compiler, then I used component & port map in my .vhd file to use the memory. But there is are some problems which I can not solve. 1- In MC output file some libraries are included : use WORK.vlibs.all; use WORK.lib_cells_pkgs.all; but when I run modelsim to generate the saif file, it doe
Hi all, I have a problem with the synthesis of leon3... I want to have the post-synthesis verilog to make simulation with modelsim, have the VCD and the saif, to use primetime for power report... everything is ok but some module's names are too long and I can't write the DDC and primetime won't go... i tried to use change_names_rules -maxlength
Hi I run a gate level simulation (SDF annotated) in modelsim 6.4a, using following script project open gls.mpf project compileall vsim -c -L CORE65LPHVT -L CORE65LPSVT -L CORE65LPLVT -noglitch -sdfmax /testbench/d3=/tmp/umair/grlib-gpl-1.0.22-b4095/designs/leon3-stm65/synopsys/leon3mp.sdf -sdfnoerror -t ps work.testbench
Hello, I'm trying to use Synopsys forward annotation saif file in modelsim to evaluate the power of my design and I have a problem. I use the following generate loop in my top: iter: for i in 0 to N-1 generate multiplier: multiplier_cell generic map ... end generate iter; Synopsys refers the the cells in the saif as (...)
Hello i'm making synthesis of a part of my design, i want to record the switching activity only of this part of design, than generate a saif file from VCD generated in modelsim. My problem is, how can I do to record the switching activity in the VCD file, for only a part of my design? "a part of my design" means that I want to recor the switch
Hello evryone can help me to record the switching activityin modelsim? I've read that is possible to record it using commands like $toggle which I can use to generate a saif fail, or using the VCD files. Is it correct? commands like $toggle can be normally used or I ve to insert a new library? Otherwise how cai I generate VCD files?
I have created the forward annotation file in dc_shell (/rtl2saif forward.saif/) and import it into modelsim by library using the command "vsim -foreign "dpfli_init /lsc/synopsys/syn-2005.09/auxx/syn/power/dpfli/lib-linux/" -c -quiet tbgen" with no problems modelsim reads ok that file but when i try to (...)
Hi, I am comparing a number of arithmetic adders based on their power consumption. I use Synopsys Design Compiler for synthesis and Prime Time PX for power analysis (using back annotated saif files, from simulation in modelsim). I can't figure out if the Synopsys tools are actually analyzing the power that is dissipated due to spurious transiti
Hi, I'd like to obtain an saif file for a VHDL circuit. I'm using Xilinx ISE 11.3 to implement my designs on FPGAs and modelsim 6.5 to simulate them. Can anyone explain how to get it starting from a VHDL source? Thank you.
Hi, Guys, I have generated Forward saif file and i want to use it to generate back-annotation saif-file. The problem is I have no idea how to read the Forward saif file into modelsim. could you help me figure it out? many thanks
u could use modelsim to dump vcd and use vcd2saif which is provided by DC to convert the vcd files to saif files.
the power compile needs back-annotated saif file after the simulation.modelsim requires the vcd file,but I cann't successufully include the vcd file which tranferred from saif file . can anybody help me? It's kind of u if u can tell me how to handle the Power Compiler with modelsim. thx
i produce vcd with modelsim by using the following code The design has been ungrouped in design analyzer and is in verilog format. initial begin $dumpfile("mullbin8.vcd"); $dumpvars(0,mullbin8); $dumpflush; end ---- I then use the saif file from the vcd with the following. current_design mullbin8 power_preserve_rtl_hier_names=true re