455 Threads found on edaboard.com: Monte Carlo
I'm gonna use monte carlo Analysis to find standard deviation for input Offset of a latched Comparator using icfb 5.10.41_USR5.90.69. the goal is to plot it against a voltage value called Common Mode Voltage. It is to some extent a parametric monte carlo analysis. But it seams this version cant sweep any (...)
Software Problems, Hints and Reviews :: 03-26-2017 18:45 :: moammadhasan :: Replies: 1 :: Views: 777
Hi All, I have a question about the Cadence operation for the MC simulation for the BGR. Normally, we can specify a temperature and run the DC analysis of a BGR to get the historgram of Vref at this temperature. However, are we able to run the MC sim with different profiles at different temperatures at the mean time?
For example, this is a measur
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 03-25-2017 05:23 :: bhl3302 :: Replies: 2 :: Views: 781
does any body know any way for doing it in cadence.What do you mean by "cadence" ?
This thread title refers "spectre".
So simply invoke montecarlo analysis of Cadence Spectre.
See "spectre -h montercarlo".
If you use Cadence Spectre in Cadence Virtuoso ADE, use ADE-XL not ADE-L.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 02-27-2017 13:10 :: pancho_hideboo :: Replies: 3 :: Views: 1095
I am trying to use ADEXL to run spectre monte carlo spectre simulations using Sungrid (SGE) for distributed (parallel) processing. However, I can't figure out how ADEXL uses the Run Options -> 'command' field to execute "qsub -q "bm.q" -cwd -V -b y -j y" . There is no output log related to sungrid, just a file that says it failed. I'm un
Analog Circuit Design :: 12-13-2016 01:09 :: peterholm :: Replies: 0 :: Views: 476
After running some monte carlo simulations in a current mirror, I would like to compute the amount of mismatch in percentage.
To compute the mismatch in percentage I should do it taking into account the (3 sigma * std. deviation) or just the std. deviation?
For example I see people saying that the current mirror has 5% of mismatc
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 10-04-2016 18:51 :: CAMALEAO :: Replies: 4 :: Views: 737
MNA-MAT, a MATLAB based analog circuit simulation tool, uses Modified Nodal Analysis to reduce a SPICE netlist to a system of equations which yield voltage at and current through specific points in the network. monte carlo analysis adds further functionality by evaluating possible uncertainties in real-world working conditions.
Business, Promotions, Advertising :: 09-02-2016 14:15 :: nik1106 :: Replies: 0 :: Views: 1028
I am running cadence virtuoso 6.1.5 and trying to sort out the monte carlo analysis for process variation and mismatch.
I want to plot the gain vs frequency plot of a single-ended amplifier for 10 runs i.e. I want to see the 10 gain-curves in a graph window.
The only option in EVAL TYPE in OUTPUT SETUP of the analysis remains fixed at "po
Software Problems, Hints and Reviews :: 09-01-2016 11:58 :: Debdut :: Replies: 0 :: Views: 723
I think studying the spice model in analysis process then set parameter in spice program to more practical and proper for purpose . Pspice has monte carlo analysis option , But no 3D graphics result shown .
RF, Microwave, Antennas and Optics :: 08-20-2016 11:15 :: phongphanp :: Replies: 3 :: Views: 1277
I would like to make a small experiment regarding current mismatch in a current mirror for different transistors area (or sizes).
I know that we have to do that using monte carlo (or maybe the dcmatch can work, I don't know). But the thing is how should I do the calculation to get the mismatch? And should I use any kind of special ci
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 08-03-2016 15:56 :: AMSA84 :: Replies: 1 :: Views: 548
It looks like you are making MC simulation with a normal lib.scs. You should add the monte-carlo lib.scs file to Model Files.
You can add the mc.lib.scs file as a new corner.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 07-28-2016 12:39 :: vadim888 :: Replies: 4 :: Views: 1076
For an LNA design, the inductors used in the design were simulated in a simulation software separate from the spectre simulator used in cadence for the other components (transistors, resistors, capacitors). So we created a n-port file for the inductors in the design and made it point to the S-parameter file generated by the inducto
Software Problems, Hints and Reviews :: 07-19-2016 17:42 :: mzzim :: Replies: 0 :: Views: 603
I have designed too many op amps and none of them have any issue with a wide range variations of supply voltage , temperature , corners of process , worst case pvt circumstances , etc . but the problem is the monte carlo analysis by which my op amps are all totally devastated .I know the monte carlo analysis has quite a (...)
Analog Circuit Design :: 07-16-2016 16:11 :: kevin_microelecrronic :: Replies: 0 :: Views: 390
Hi! I am trying to model an Arbiter PUF in Hspice. You can google it if you don't know what that is. So I am trying to implement the delay differences in the multiplexers due to process variations. In order to do that I have to run monte carlo simulations using hspice and vary the oxide thickness and the threshold voltage of the mux's to get the de
Software Problems, Hints and Reviews :: 07-04-2016 09:36 :: kanishk29 :: Replies: 0 :: Views: 935
I am trying to run monte carlo analysis on a variable, from veriloga model.
I had initially done the implementation with cadence-spectre flow. below is the example of how it is achieved in cadence-spectre. I put it here, so i can explain clearly what I want.
1. included the following in verilogA model for the variable of in
ASIC Design Methodologies and Tools (Digital) :: 06-15-2016 08:27 :: aarthy_maya :: Replies: 0 :: Views: 631
Has anyone used BJT available in TSMC65? There are pnp and npn transistors in the library and can be used.
I wonder if any one has simulated monte carlo for those BJT. For MOS, one should replace "_mac" transistor and add "stat_mis" library. How about BJT? there is no "_mac" file to be replaced!
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 05-18-2016 00:38 :: vaah :: Replies: 1 :: Views: 597
I'm trying to solve a problem I was tasked with.
Basically I have to generate a 100k 16QAM inputs and transmit them over a AWGN channel.
With this I have to use the monte-carlo estimation to figure out the mutual information.
I was told to use this estimation:
So I generated the input vector, the
Digital communication :: 05-15-2016 17:02 :: knoluis :: Replies: 0 :: Views: 605
I am trying to run the monte carlo analysis of the offset voltage of a comparator.
For this, I am using the 'cross' function from Cadence calculator. The expression I use is the following one:
cross(VDC("/OUT_SF") 0.9 0 "either" t "time"),
where OUT_SF is the output of my comparator and 0.9 is my threshold value. Befo
ASIC Design Methodologies and Tools (Digital) :: 04-08-2016 10:08 :: evilella :: Replies: 2 :: Views: 1408
Im using Cadence 6.1.3 and Id like to do monte carlo simulation. I found out that "m" shouldnt be used in schematic or monte carlo might be errorous. source:
So I decided to test it:
ASIC Design Methodologies and Tools (Digital) :: 03-29-2016 19:22 :: Gornarok :: Replies: 1 :: Views: 620
I have used Synopsys Star RC tool to obtain a .spf file. My question is how to use that .spf file in HSPICE to perform monte carlo analysis? Thank you.
ASIC Design Methodologies and Tools (Digital) :: 03-22-2016 06:12 :: RangerSunstrider :: Replies: 0 :: Views: 625
It will likely work close to your simulation results if you follow proper design procedures such as a good layout, heat sinking, and supply decoupling, but no guarantee.
If you can, do some monte carlo simulation multiple runs to see how component variations (including supply voltage variation and offset) affects the amp performance (I assume thi
Analog Circuit Design :: 03-20-2016 08:18 :: crutschow :: Replies: 14 :: Views: 1611