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Mos Varactor Design

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11 Threads found on edaboard.com: Mos Varactor Design
Dear all Have you used the mos varactor in the LCVCO design. There are Nmos varactor and Pmos varactor, what is the difference of them, and which type of varactor is fit for the LCVCO design. Thank you very much.
Hi, I meet a problem when I layout a mos varactor using ST 0.12um designkit. The Pmos varactor is formed by connecting S and D together. But when extracting, there is an error telling me 'Cannot match terminal counts for phsmos4 ...' Because this designkit is used for (...)
You can use the varactor cap(nmos in nwell) as PLL loop filter cap. BR eric 1/4
Dear All : I read some paper about Nmos with Nwell mos. It is use in varactor. A-mos .If I want to use the cap in the LNA design . Does anyone have do it ? Actually we always check the P1dB or IIP3 . Does any good method to check the linearity ? Thanks
Hi you can refer to Tsividis's works such as: "Operation and Modeling of the mos Transistor," Yannis Tsividis as well to the best paper entitled: "0.5-V Analog Circuit Techniques and Their Application in OTA and Filter design," by Chatterjee, Tsividis and Kinget to find out making varactors in most famous configs. and (...)
try to make the varactor is parallel mos transistors with M devices , this will make the quality factor of the varactor better coz parallel devices will make less gate resistance of the varactor khouly
How can i extract the gate- capacitance variation of the mos transistor, in the Cadence analog design enviroment, dc signal analysis?? Im using the varactor in a LC VCO design, and want to get a good as possible estimation of the ideal LC tuning characteristics. -Saber
Hi: If you are using LC-VCO, with mos varactor tuning, parameters such as phase noise, VCO sensitivity, output power level, frequency pushing, frequency pulling and tuning percentage is of importance. Rgds
Hi all, Today I read a sentence in the IBM design menu. It says for the mos varactor device, when the Vg-d is below -0.5V (eg. vg=0.1V, Vsub=0V, Vd/s=0.7V), the capacitance could become unstable. That is scary. I have never seen this in other foundry's design menu (tsmc/umc/jazz). Does anyone know if this (...)
how to get the combine Q in VCO design?
Try these papers from IEEE and others, I don't have them however here. 1.) P. Andreani and S. Mattisson, ?On the Use of mos varactors in RF VCO?s,? IEEE J. of Solid-State Circuits, vol. 35, no. 6, June 2000, pp. 905-910. 2.) A-S Porret, T. Melly, C. Enz, and E. Vittoz, ?design of High-Q varactors for Low-Power Wireless (...)