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Hello, My goal is to find out how to synthesis and place&routing is affected after small modifications to an existing VHDL code. After a small change (e.g. halving the threshold frequency) in a bigger structure, I have to make sure that the not changed parts of the code post P&R should stay the same and be equivalent, s
Dea Forum Im designing a FIR filter, in this case a low pass. I get the coefficients from Matlab (no matter from where..) ,that are from 0 to 1, in floating point. Now, I want to implement this FIR in my fpga ,with buil in 18x18 multiplier. So,I transform the coefficient in integer value of max 17 bit (1 bit for sign) ,multipling (...)
I have question How can we send multiple bytes via UART?, What happen if we want to send multiple bytes assume want to send 8 bytes ? If I want to send one byte data, I can send like : start-byte1-stop //send one byte Can we send like this start -> byte1-byte2-byte3-byte4-byte5-byte6-byte7-byte8-stop //
Hi, I am working with a project having around 70 DDR LVDS 910 Mbps connections to fpga. I am wondering if ZYNQ 7Z030 have enough LVDS IOs with at least 910 Mbps ? Another question, as there are two Ethernet Controllers in ZYNQ 7Z030, does this means that no Ethernet controller chip is required on the PCB and only Ethernet PHY port is needed
Hi I want to combine 8 loop antennas into one structure, each of them at a different angle to the others. By using 8 relays, I want to select each of these 8 loops so that I can null a signal at a wanted direction. So instead of using a single loop and a rotor, to use multiple loops and select each of them. Now the problem I have is that I have on
Hi, I am new in this field. I have rtl code of an IP. Now I want to implement wrappers around the i/o ports. Can you please suggest me how to do that? Do i need to write rtl code for the wrappers as well or any other means are available? Thanks in advance.
Hello in new year 2020 ;-) After severals experiments with few soft-CPU (Picoblaze, Microblaze, RISC-V) I decided to try implementation of AVR core (ATMega103) from - see choosed this core because it seems to be complete and h
Hi, You have to say how it relates, because we don't know. And this lack of information makes it impossible to abswer the question "what is best". multiple LEDs will cause multiple sources of light. Single lense or multiple lenses ... it now depends on focus adjustment whether you get one big blur spot or multiple sharp (...)
Hi, can anyone recommend an EVN or stacked fpga system for capturing a still image? preferred 720p. I would like to trigger a snapshot - freeze the video and transfer the image via USB to a PC (via FTDI or Cypress USB chipset). The picture should only be transferred once the trigger occurred. This would be my first application with a camera
Hi, Any one working with multi-layer PCB he is forced to get an 90W adjustable soldering iron. In our company we design multilayer PCB, do prototype soldering, rework, repair, low volume production. In our whole company we only have soldering stations up to 50W. Mainly we use Weller WECP-20 antistatic with MLR-21, or LR-21. Tempe
You should ask yourself what you consider wrong data? 1. Single bit data, toggling at arbitrary times. You'll either read the old or the new data. Both or equally correct, just different. 2. A multibit entity. Individual bits can be expected to have a certain skew. If you manage to sample a data word while the value is changing, you may get a
I'm looking for old Altera EPM7128SL fpgas. On ebay there are many at a bargain price, but I don't trust them. Could you give me some advice on where to buy them?
Hi, What do you think is the fastest multiplication alghorithms in the world?
You don't say what interfaces you have available to use on your STM32 nor the nature of your data (sequential vs random access) ? Bear in mind an fpga can be designed to interface to practically anything so your MCU is the limiting device. I am working on some kind of vector floating-point coprocessor. I would
Hi All, am appealing to anybody who has a similar environment to give me a few tips here :) The internet problem is weird, the system default is ffox 70 that runs fine standalone but none of the quartus menu's that would invoke it (help etc) work you just get no response. The same is true even if you set the browser path directly to ffox instead
Hello Guys, I would like to ask for opinion. For some time I am looking for cheap fpga board with big number of "logic cells" and "DSP blocks". I do not need very high clock frequency and super speed comunication capabilities. I think "bigger" represenstant of Artix-7 or Spartan7 families would be enough. I am experimenting with some kind of vec
Can you please tell me any three important differences between Artix 7 xc7a35tcpg236-1 vs Stratix III EP3SL150F1152C2 fpga. It is going to be helpful for my exam.
Hello, as far as I understood you correctly - you waana design a matrix multiplier (2 dimensional arrays). You don't give many important assumptuions related to your design. We don't know how big can this matrices be? We aslo don't know how is type of data in these matrices - are them fixed-point or floating-point numbers. You are trying compare
A short article on the design of the push-pull transformer: These are very problematic for newbies in power electronics, principally because in a classic topology there are 2 issues that dominate, namely; 1) leakage inductance &, 2) flux balance in the core - i.e. stair-casing of flux / Imag to failure. Many newb
I wrote a verilog code of a counter and after implementation in fpga board I came to know that it can work with a clock rate of 50 MHz. Whether it is needed to set the same clock frequency in the constraint file during synthesis using Cadence Genus tool. What happen if I will increase the clock frequency to 100 MHz, during cadence genus synthesis.