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271 Threads found on edaboard.com: Multiple Power
powers must be in linear units (i.e. watts), doesen't matter if you use multiple or submultiples but Pr and Pf must be espressed in the same units. f.i Pr in W and Pf in W Pr in uW and Pf in uW and so on. However your case is not a real one, since the reflected power is higher than the forward (...)
Most MMICs have the bottom side grounded. "Bondwires connected to ground" is typically not necessary. Running multiple bondwires in parallel is to reduce parasitic effects of bond wire and/or increase power handling capabilities. Could you attach the datasheet?
Dear all, For some reasons, i can't do the balance clock tree in back-end. Instead, I need to balance in synopsys dc_shell. My problem is: There are two cpu clock domains, clk1 and clk2, both running at 25Mhz. They are from the same source, clktop, but have different control due to some power saving mode to disable the 2 clocks. However, some
Hi, For ICs having multiple power pins (say 1 analog and 1 power ground), how is the ESD setup for "pin to gnd" test? Do they need to test it separately or Agnd & Pgnd need to be shorted in the test? Thanks!
The first paragraph on the antenna theory page has multiple errors. Interestingly though the paragraph right below figure 1 does get the relationship right. In the above Figure, S21 represents the power received at antenna 2 relative to the power input to antenna 1. For instance, S21=0 dB implies that all the power (...)
I don't agree with the initial premise. .............but surely most power supplies that supply test equipment are isolated, so it simply will not matter to which node one connects the scope probe "ground" clip?...and no such current will flow in the scope probe wire - most D.U.T. have multiple connections, e.g data lines, other gr
Hi mkelly, I dodn't understand why you have 2 diodes D4 and D5 on the output. They will just degrade your load regulation and make your output voltage very inaccurate. Also from the LM317 datasheet I see the Theta jA is 53C/W so with an ambient temperature of even 50C you can only dissipate (15
Dear Hayoula, There can be other methods, but in my experience we delaed with those type thing as below: 1 - If the cell is designed such that it is multiple of the row height, the placer should be ablet to place it (I know that Magma Blast, SOC Encounter and ICC can do this type of placement). - In this case the power pins of cell should fo
Have a look at the MWO examples and search for "extract". There are multiple examples where EM extraction is shown for power dividers.
I just couldn't get this sentence that I take from Rappaport book on Wireless communication in the chapter on "multiple Access"- "In wideband systems, the transmission bandwidth of a single channel is much larger than the coherence bandwidth of the channel. Thus, multipath fading does not greatly vary the received signal power within a wideb
Size and cost are two that immediately come to mind. Capacitors also are only effective at filtering signals over a certain range, then their package parasitic dominate and they don't look like caps anymore. That's why you'll often see multiple caps on power pins of digital devices... like a 1 uF, 0.1 uF, 0.01 uF and ana 0.001 uF all in parallel.
hi to all... i am designing a switch mode power supply using push-pull. i want different voltages like 5 and 3 with 12V. A friend told me about the coupled inductor that it is a solution. i dont have any knowledge about the coupled inductor. i just want help to do this stuff... my input is 24 volts and im using sg3525 for pwm. the mai
I'm designing a DDS-based general purpose signal generator for my home lab, based around a dsPIC, two AD5930S DDS chips and a lot of assorted op amps for filtering, level-shifting, VGA, etc. It uses a 5V digital rail, and +/-5V and +/-15V analogue rails. All are planned to be linear, not SMPS, to keep noise sources away as much as possible. The
Not that I'm aware of. Why exactly do you need multiple, regulated outputs? Do they need to be isolated from each other (so you also need isolated unregulated supplies if that's the case)? There's probably another way around the problem.
You need to consider: required accuracy, drift, cost, second-sources, package, required external components, power dissipation, etc. There are probably multiple types that would work for a given situation, but not all types work for all situations. Maybe some things don't matter; pick that ones that do, and go from there.
Hi everyone, Is there a way to connect multiple drivers to a single port in FPGA synthesis. Here is a sample code: ... signal out: std_logic_vector (7 downto 0); signal in1: std_logic_vector (7 downto 0); signal in2: std_logic_vector (7 downto 0); signal in3: std_logic_vector (7 downto 0); out <= in1; out <= in2; out <= in3; .
My basic problem is that I would like to clock my FPGA at a very specific frequency multiple (over a million) of an incoming signal. This incoming signal is wall power, so it is 60 Hz, plus or minus, and slowly varying. My original approach was to purchase a VXCO at this frequency that had the largest pull range I could find (+/-200ppm), divide t
Hi I am looking at using multiple 18s20 devices in a monitoring unit, I was thinking of using parastic power for the device. Has any one used this mode? Is so make what is the max cable distance used ? What number of devices? Thanks
PIC16F193X/PIC16F194X This MCU family ranges from 28- to 64-pins and features low power nanoWatt XLP Technology, segmented LCD driver peripheral, capacitive touch module, EUSART, SPI, I2C, multiple PWMs, multiple timers.
Read datasheet of mosfet to see working temp and amperage. 200A is to high for that single package. Maybe you need paralleling multiple of mosfets. In datasheet given power (amperage) is at 25C of working temp, see temp/amperage curve in datasheet. Its very difficult to stay at this level of temperature for such high amperage. Make calc for