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271 Threads found on edaboard.com: Multiple Power
Before my question this is the assumption - I am assuming Supply sequencing is same - within ASIC which has many power domains, and within ICs which are sitting on Board. 1. What is the need of supply sequencing within ASIC which has multiple power domains. 2. If we don't follow it what are the violations? 3. How to catch them during (...)
1024 is because it is a power of 2. As binary numbers double in size each time you add a bit, the progression is 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2014, 4096, 8192. That means you can select all the addresses up to 8192 using 12 bits, if you used decimal 1000 as size multiple, you would not be able to reach all the addresses without ad
Bootstrapping with a proper driver solves the problem of high side gate drive supply with minimal components. There are a few cases you can't use it, but I don't see anything to indicate this is one of them. Yes, the "approach" of the original post is however to use a single, non-isolated power supply for multiple high side driver
CDMA came from Code Division multiple Access. Each mobile use different code and the base station is able to differentiate the users by their code (and not by power, time, etc.)
When doing a Boundary conduction mode PFC stage, ive always gone on the thermal test of the electrolytic capacitor at the BCM PFC output as being king. However, the current ripple in the PFC?s output capacitor has components at the switching frequency (say 70kHz). ?but also has a significant component at the twice line frequency (100Hz), due t
Yes, and the Output can be Either Stepped UP or Down in Voltage. You could also have multiple Output Windings. Your Biggest Problem is Making a SUITABLE Ferrite Core Transformer for the Frequency of Operation. Typically it should be wound with LITZ Wire, to better handle the High Frequencies involved.
if the problem is that I aren't able to do a analog read within the while loop, (which I have to do anyway), could I just not do it within the while loop? Presume the processor has enough computing power to perform multiple actions virtually parallel, e.g. reading analog values and generating an accelerated step motor control seq
Dear all, I have a synthesized gate-level netlist and need to provide it with multiple input test pattern and extract the total power consumption of the whole circuit during the circuit operation (I want to plot the power consumption of the circuit while its input test patterns are changed). Is this task possible in SOC encounter? If so, (...)
IEC 1000-3-2 (limits for harmonic current emissions) defines conditions for harmonic measurements using DFT in appendix B.4. It assumes that the measurement window is synchronized to the mains period and an integer multiple of it.
I am working on a project where I need to measure the current drawn by multiple loads from a single power supply using a 8-bit PIC micro-controller. Also, when an overload condition is detected in any of the loads, I need to cut it off using a MOSFET. Here, each port is limited to a specific current and the sum of all the port current is the total
I wanted to use ac source in my diy soldering station, i found a 24v 3 amp transformer but the problem is i am not able to figure out the pinouts for it. I will upload a pic of it so that you may know how it looks. Thanks in Advance Unmesh. 130974
If matched perfectly, multiple transducers can at best share the total 800 W generator power. So in any case, the power per transducer and respectively the welding "power" will be reduced. Is this what you want?
Hi Sir, I have a nrf24L01 module acting as a transmitter and multiple other nRF's acting as receivers. And every receiver has to receive data from Tx. How can synchronization be done between 1 Tx and multiple Rx's so as to reduce Nrf's power consumption. Any help is much appreciated. Thanks
Also, how common are phased array antennas with multiple 1cm^2 patch antennas....each antenna being driven by an ASIC. I presume this is very common?
Hi, I have designed a circuit using using op-amps, comparators, diodes and transistor. It uses 15 and 5 volts supply, but during my test I have accidentally supplied 15V for the whole circuit system, and after that the two supply inputs appears to be shorted. Whenever I applied the two supplies together, the 5 Volts power supply is pulled up to 15V
High Vth in power FETs means a high gate voltage swing means high switching losses. In IC technology, you have to position VT to best deal with the leakage power vs drive strength / speed "box". Here you often see multiple VTs in the same flow so that you can optimize near-static logic, and high speed clocked circuitry separately. An (...)
When I put in more than 1 opamp the power pins are connected and in most cases that is fine. In my current circuit I am implementing a linear optocoupler (HCNR200) to isolate HV from LV circuits and I want the opamps on different supplies. I cant find a way to disconnect the power pins. It is not critical as I am able to disregard the non-route
I recommend letting the uC drive a power MOSFET driver IC (best, through some buffering that can break any ground loops) which can be had at multiple amps of output drive and take 12V easily.
It will likely work close to your simulation results if you follow proper design procedures such as a good layout, heat sinking, and supply decoupling, but no guarantee. If you can, do some Monte Carlo simulation multiple runs to see how component variations (including supply voltage variation and offset) affects the amp performance (I assume thi
The question can't be answered generally. In many cases it's OK to use split power planes as ground for embedded strip lines or differential pairs. I did it quite often in mixed signal designs, there are however some prerequisites: - power planes have multiple low inductance bypass capacitors distributed over the board area - (...)