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61 Threads found on Multiplier And Verilog
I have written a code for GF(16) multiplier in XILINX but i am getting some errors.plz help me. 135472 module mult4_4( input a, input b, output p0,p1,p2,p3,p4,p5,p6,p7 ); wirew; wires; wirec; and(w,a,b); and(w,a,b);
I have written a code for GF(16) multiplier in XILINX but i am getting some errors.plz help me. 135474 module mult4_4( input a, input b, output p0,p1,p2,p3,p4,p5,p6,p7 ); wirew; wires; wirec; and(w,a,b); and(w,a,b); and(w,a,b
just out of curiosity, how do you guys do math in FPGA? Take multiplication for example, I always invoke IPcore, except when come coefficients are constants then I'd use shift and add. As to other operations such as cordic...IPcore is my first choice... Multiplication I almost always do as a * b. It makes for
Hi, I am using Primetime to perform Voltage scaling, then i need to get timing and power change. When I use set_voltage, i can see changes in power, timing remains the same. I have a combinational multiplier design. No clocks in verilog code. I am trying to use set_rail_voltage, but i dont know clear way. I am trying to use the following (...)
Dear all I need to instantiate an Altera float-point matrix multiplier megafunction in my design, and plan to implement it with a one-hot state machine. The problem is that the filed generated by the quartus megafunction wizard have errors, such as in the .v (I use verilog) file there is Error (272006): MGL_INTERNAL_ERROR: Port (...)
i have this code and wanna to update it to multiply 4 by 3 bits any help :) thanx in advance // // // // // This file is part of the Amber project // // //
I am a beginner when it comes to verilog and i have found this 32 bit multiplier code(using CSLA logic:it seems, thats what a friend of mine said). Is there a way to reduce the code: i mean by using for loops or any other method. I am doing this for my academic project and i need some expert help if there is a way i can (...)
Hey all, I was wondering if you could help me with my homework. I need to implement a 4-bit multiplier at the gate-level in verilog using and gates and adders I've drawn the layout, but I'm having trouble translating it to verilog. When I instantiate an and-gate, how do I extract (...)
can anyone help me build a 5x5 bit signed multiplier.. im a beginner and im trying to program it in altera Quartus II
I am trying to implement a floating point multiplier on spartan3E using verilog. and I want to display the result in LCD(spartan3E 16x2 LCD). How can we convert floating point to integer format in verilog? How can we display the floating point number in LCD? and also I wand to give input (...)
i need code and block diagram for implementation of 16bit multiplication using carry save adder urgently. Can someone please help me out.
I am designing (256x256)-bit multiplier using DSP blocks available on Xilinx FPGAs. I split operands into several chunks of 64-bits, using Karatsuba technique 256-bit multiplier can be constructed using 3, 128-bit multipliers each of which are further realized by 3, 64-bit multipliers. i have constructed (...)
how to calculate the total delay when no. of clocks are used in verilog code and help me out to write the code for 8 bit wallace tree multiplier in verilog
I am trying to build a ripple carry adder using a hierarchical verilog structure description. What I have is not working right... out puts are all messed up. My logic is messed up somewhere but not sure where. I grabbed the test bench from a 8 bit multiplier to use for the RCA and so I know I am overlooking something basic... any help (...)
Hi all, Please provide me some valuable inputs regarding multiplier using shift and add method in verilog. say : multiplicand and multiplier be two inputs of 8 and 6 bits respectively. and it should follow 2's compliment of positive numbers Note :- (...)
90236 I am trying to implement a sequential shift and add 4bit multiplier as shown in the image. I am having a separate module for the 4 bit ripple carry adder. I have tested the adder module and it works fine. now i need to trigger it from the multiplier module. so that it triggers on the 'add' signal. please help
Hello. I am working with QuartusII. My project is Serial Mutrix multiplier and I use verilog, but when i compile my project the following error appears.Can you help me? Internal Error: Sub-system: GDFX, File: /quartus/synth/gdfx/gdfx_slice.cpp, Line: 736 (*sgate_nodes) != NULL && (*sgate_oterm_coll) != NULL Quartus II Vers
i need to design a multiplier unit.. design idea: only binary inputs representation signed representation..can provide a sign bit input.. ie.. if we want to multiply 2 and -3.. input given should be 0010 and 0011(consider 4 bit numbers)..since sign of one of the number is negative..i can give a sign bit input as 1 here.. so i need a program
Hi, my code currently looks like this. Is there any way my code can accept non integer numbers (A=3.05). I read that my output has to be a reg type so how can we represent multiplication, division or addition using non integers? For ex. 3.05 + 1.07 or 1.06*5.01. If the output must be of type reg. I read online that there are very complicate
hi can u send verilog or vhdl coding of 4x4 bit braun multiplier and 4x4 baugh wooley multiplier