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114 Threads found on edaboard.com: Multiplier Verilog
I have written a code for GF(16) multiplier in XILINX but i am getting some errors.plz help me. 135472 module mult4_4( input a, input b, output p0,p1,p2,p3,p4,p5,p6,p7 ); wirew; wires; wirec; and(w,a,b); and(w,a,b);
I have written a code for GF(16) multiplier in XILINX but i am getting some errors.plz help me. 135474 module mult4_4( input a, input b, output p0,p1,p2,p3,p4,p5,p6,p7 ); wirew; wires; wirec; and(w,a,b); and(w,a,b); and(w,a,b
just out of curiosity, how do you guys do math in FPGA? Take multiplication for example, I always invoke IPcore, except when come coefficients are constants then I'd use shift and add. As to other operations such as cordic...IPcore is my first choice... Multiplication I almost always do as a * b. It makes for
Hi, I am using Primetime to perform Voltage scaling, then i need to get timing and power change. When I use set_voltage, i can see changes in power, timing remains the same. I have a combinational multiplier design. No clocks in verilog code. I am trying to use set_rail_voltage, but i dont know clear way. I am trying to use the following code set
Dear all I need to instantiate an Altera float-point matrix multiplier megafunction in my design, and plan to implement it with a one-hot state machine. The problem is that the filed generated by the quartus megafunction wizard have errors, such as in the .v (I use verilog) file there is Error (272006): MGL_INTERNAL_ERROR: Port altfp_matrix_mult|
i have this code and wanna to update it to multiply 4 by 3 bits any help :) thanx in advance // // // // // This file is part of the Amber project // // //
I came across a verilog example of improving power consumption in a multiplier. The original code is reg Enable; reg A, B, DataOut, MultOut, AddOut; wire A, B; always@(posedge clock) if (Enable == 1) DataOut <= MultOut; else DataOut <= AddOut; assign MultOut = A * B; assign AddOut = A + B; The assumption
As vGootimes said the FPGA equivalent to the huge, un-maintainable mess of structural verilog, would be this: module multiplier ( input a, input b, output p ); assign p = a * b; endmodule But if you want high performance you'll probably want to add a clock and include some pipeline registe
please share the code for fft computation. We have written the code for 8 bit vedic multiplier(urdhva tiryakbyham).
Unfortunate the floating point vendor libraries aren't provided as VHDL sources, most likely they even haven't been written in VHDL or verilog. They are designed to use the DSP hardware of different FPGA families in an optimal way, using respective low-level primitives. Altera e.g. is typically writing this stuff in AHDL. For the same reason, wr
Hey all, I was wondering if you could help me with my homework. I need to implement a 4-bit multiplier at the gate-level in verilog using AND gates and adders I've drawn the layout, but I'm having trouble translating it to verilog. When I instantiate an AND-gate, how do I extract the least significant bit from the AND's output? (...)
Hi, I'm trying to code a signed multiplier, and I used 'signed' for the ports and wire, but when I run (ModelSim) simulation to check it, it doesn't work for me. Below is the code and the simple testbench. The numbers are the most positive (0xFF) * most negative (0x2000). In simulation, I get 0x1FE000, which is not the correct answer. Any idea
can anyone help me build a 5x5 bit signed multiplier.. im a beginner and im trying to program it in altera Quartus II
I am trying to implement a floating point multiplier on spartan3E using verilog. And I want to display the result in LCD(spartan3E 16x2 LCD). How can we convert floating point to integer format in verilog? How can we display the floating point number in LCD? And also I wand to give input to the multiplier through a (...)
i need code and block diagram for implementation of 16bit multiplication using carry save adder urgently. Can someone please help me out.
Can anyone go over my code really quickly and see what I am screwing up? I am trying to implement a 8x8 sequential multiplier using a finite state machine. This is using the add + shift product method. Thank you so much for any tips / pointers! module MULTIPLY_revision ( input clk, reset, start, input A, B, output reg don
I am designing (256x256)-bit multiplier using DSP blocks available on Xilinx FPGAs. I split operands into several chunks of 64-bits, using Karatsuba technique 256-bit multiplier can be constructed using 3, 128-bit multipliers each of which are further realized by 3, 64-bit multipliers. i have constructed 64-bit (...)
Hi, I'm looking for a verilog code for array multipliers(8,16-bit) can anyone plz help me out...i'm having trouble writing the code plz help me out... Thank you
how to calculate the total delay when no. of clocks are used in verilog code and help me out to write the code for 8 bit wallace tree multiplier in verilog
Are you asking about a parameterizable module, where the bit length of some inputs is defined by a parameter, or do you mean that the length is variable at runtime? A generate construct can only work for the first case. generate if (SIZEPAR == 8) // instantiate 8x8 multiplier else // instantiate 4x4 mutiplier endgenerate