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20 Threads found on Nanosim Error
Hi all, I used synopsys nanosim to simulate verilog netlist. The verilog netlist is generated from DC. But when I run the nanosim, the segmentation faults came out. What are these faults mean? How can I solve these?? Thanks for any help!!!
Hi all My tools environment is : installv3.0 , scl10.9.3 vcs2012, nanosim2012 I have already run vco of nanosim examples, it's passed. But when I run NS-VCS in tutorial of nanosim examples, there was a error after "simv +COMPILE" command: ***** Warning: Stacksize soft limit 10240 K is too small, we prefer more (...)
hi guys, I am going to convert fsdb file to pwl file by nWave (the software integrated in nanosim).I do exactly as the user guide says.For example ,I want to convert signal v(I3_Y) in XI1 to pwl and I input follwing code in Linux shell "fsdb2ns aa.fsdb -o a.pwl -s "XI1.v(I3_Y)" but it does not worked ,it hint this "*error* Assertion failed,file
I am compiling 4-5 hspice files of TSMC65LP using nanosim. In one file I am getting this error: error:nanosim:0x30201054:File "tpzn65lpgv2_1_2.spi", line 424, column 0, format SPICE: Can't locate resistor model error:nanosim:0x30201054:File "tpzn65lpgv2_1_2.spi", line 425, column 0, (...)
Hi I am trying to simulate a spice netlist through a spice testbench in nanosim, but I keep getting the error highlighted in red below. The spice netlist was generated using Design Architect by Mentor graphics using tsmc018 technology. I call this netlist in the tesbench I created. The spice test bench is given to nanosim. (...)
:-P Hello everyone here, I am a new one in this forum. I have a question about nanosim. When my simulation is almost about to finish, there shows an violation!!! 100% done segmentation violation signal-11 ... Nomatter how hard I try, it just shows up again!!! Can any one help me with it , Thanks a lot~ :-):-):-)
Hi Guys, I'm new in nanosim, and I'm confronting with the message: nanosim: error: No supported SPICE models found and no technology file specified... Everything is correct: - my circuit (well synthesized) - gates in circuit are well specified - def. of transistors as well - supply + config - spec. top Does any-one has an (...)
Hi, I am working on design simulation using nanosim, and am facing this error below. WARNING:nanosim:0x202040aa:s is unused port in instance "xrx3/x12/r0" of subckt "rdiffp3". The netlist used for nanosim was obtained from Calibre PEX. When I referred to the instance "xrx3/x12/r0" in the hspice netlist, it was given (...)
error:nanosim:0x30201054:File "./netlist.sp", line 783, column 0, format SPICE: Can't locate resistor model open file "netlist.sp" and go to line 783 .. copy paste that line in forum... i may be able to answer your problem....
Hi ALL, Recently, I faced a probelm when using nanosim. First, I have a Spice top-netlist. In this netlist, I will define all the analog blocks. And also call some digital blocks. And those digital blocks were define in another VERILOG netlist. How should I run my simulation? I keep getting the error below. I dont know how to sol
Hi ALL, I am new to nanosim. And now try now trying to setup for a simulation. But, unluckily, my setup some how got problem. The error message was like this: error:nanosim:0x30201054:File "./testchip.sp", line 98, column 19, format SPICE: syntax error In file testchip.sp, line 98, column 19 (...)
Hello I used nanosim last week first. so I don't know about nanosim I have a question. In nanosim, How to use HSPICE rule file in nanosim netlist? for example, when I execute nanosim, following error message was listed. (...)
Run nanosim,got this error: ...... Number of residual dc events scheduled : 1 Number of ic nodes scheduled : 0 DC initialization took 15.340 s nanosim: fsdb.c:135: build_fsdb_scope_tree: Assertion `SORT != ((void *)0)' failed. /usr/local/eda/ns/linux/ns/bin//scripts/nanosim: line 1033: (...)
hello everyone! I have a problem in the nanosim simulator. when ever i run the script, it give the message "error: Parsing netlist failed. Program exits." Can somebody help me? i can't find the error. Thanks a lot!
In using HSIM ( or nanosim), HSIMVCD2VEC command converts VCD file to Stimulus Input signal easily. Analog & Digital Block were easily simulated by this way. question : I written SIG (signal information file) like this #format % #scope tc_top #in RESETB and I extracted VCD file from verilog. But I get an error log file l
Hi, What is the error reported by nanosim. Thnx.
Hy guys Which of these ERC ( error rule checkers ) do you prefere for DRC extraction of a layout. Anybody has experience with nanosim DRC checker ( personaaly I've only experience with DRACULA DRC). ? I mean for example if some of you have experience in checking a layout with nanosim and dracula and one off these checkers doesn'
I'm using nanosimgui to verify mixed-signal circuits,I do everything follow the manuals,but nanosimgui keep saying that "n18 can not be located", n18 is one of the models in spice lib,but the .lib&.mdl files had been compiled as the Log said. Besides,I can simulated analog circuits successfully bu nanosim,but when came to Mixed,I failed (...)
Does nanosim2003.03 support RH7.3 ? Anyone succeeds in installing it on RH7.3 ? I have tried but cannot invoke the program. Hi 1. Would you please specify the error status? 2. nanosim have a little bit of post-installation problems. One is: after installation you have'nt see ./bin directory and you see only ./exec di
When I use tsmc's rf018.scs model library in nanosim simulation it reports that syntex error. Does anyone know the reason?