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5 Threads found on Nanosim Vcd
I am a student, working on Digital IC design. When I used nanosim for Post-Layout simulation, it generates a lot of state comparison errors. The inputs to nanosim are 1. hspiceD netlist generated from Cadence Virtuoso extracted view from Layout. 2. Vector file generated from vcd file (obtained by NCVerilog simulation of the verilog (...)
you can use the same testbench which used for post layout netlist simualtion for nanosim rather than the vcd file. I guess input test vectors are not driving it. BTW is it DFT simulation?
Hi all, I wish to do a nanosim fast spice simulation. I am confused about how to do this. I have the SPEF file, .mod file, the gate-level verilog netlist and a test-bench. Is it possible to use the test-bench directly or must I generate a .vcd file and then convert the .vcd file to .vec file with the vcd2vec (...)
In using HSIM ( or nanosim), HSIMvcd2VEC command converts vcd file to Stimulus Input signal easily. Analog & Digital Block were easily simulated by this way. question : I written SIG (signal information file) like this #format % #scope tc_top #in RESETB and I extracted vcd file from verilog. But I get an (...)
hello , all I want to translate my vcd file to vec file so as to read in nanosim . I found the vcd2vec command , vcd2vec <-d > -nvcd vcd_file <-nsig sig_file> <-nvec vec_file> because i'm a newbie , i don't know what is the signal information file ,just found some syntax about this (...)