Search Engine


Add Question

158 Threads found on Nanosim
Hello, I'm a little confused with doing simulations in nanosim. I have a spice netlist that I am simulating. I have connected a dummmy voltage source to my gates and want to use it to calculate current. When I use a normal stimulus file like so: VIn1 ptext Gnd PWL 0.0N 0 19.9N 0 + 20.0N 0 29.9N 0 30.0N 0 39.9N 0 40.0N 1.2 49
Hi all, I have some problem when I use the ns_vcs tool. Q1. I am able to simulate the whole chip including digital and analog part, so I think the flow is correct. There is a spice mode of SRAM in my design, it takes a lot of time to simulate. I want to accelerate the simulation by using hierarchical array reduction (HAR) in nanosim.
Hi all, I used synopsys nanosim to simulate verilog netlist. The verilog netlist is generated from DC. But when I run the nanosim, the segmentation faults came out. What are these faults mean? How can I solve these?? Thanks for any help!!!
Hi all My tools environment is : installv3.0 , scl10.9.3 vcs2012, nanosim2012 I have already run vco of nanosim examples, it's passed. But when I run NS-VCS in tutorial of nanosim examples, there was a error after "simv +COMPILE" command: ***** Warning: Stacksize soft limit 10240 K is too small, we prefer more than 60000 K, (...)
I have a SPICE netlist which prints out the voltage of a node. I simulate this SPICE netlist using HSPICE. The .lis file generated by HSPICE gives me the values of this node with a constant sampling rate. For example, I simulate from 0ns to 10ns. HSPICE prints out the voltage of the node every 0.002ns. This sampling rate is constant across all si
Hello All, I am trying to do power measurements using spice simulators. hspice and nanosim are outputting power values 2e-06 where as xa simulator is outputting 2e-12. I am confused with this vast difference. I need a fast simulation so I need to go with xa simulator but I am not really sure if I could stick with the xa simulators power values.
Hello! I get a Verilog netlist after synthesis and convert it Spice netlist by nettran, I want use this Spice netlist inputting nanosim for simulation. But some problems in the Spice netlist: 1. The Verilog netlist hasn't power and ground connections, so in the Spice netlist also missing the connections. What can I do add the connections during
hi guys, I am going to convert fsdb file to pwl file by nWave (the software integrated in nanosim).I do exactly as the user guide says.For example ,I want to convert signal v(I3_Y) in XI1 to pwl and I input follwing code in Linux shell "fsdb2ns aa.fsdb -o a.pwl -s "XI1.v(I3_Y)" but it does not worked ,it hint this "*ERROR* Assertion failed,file
I am compiling 4-5 hspice files of TSMC65LP using nanosim. In one file I am getting this error: ERROR:nanosim:0x30201054:File "tpzn65lpgv2_1_2.spi", line 424, column 0, format SPICE: Can't locate resistor model ERROR:nanosim:0x30201054:File "tpzn65lpgv2_1_2.spi", line 425, column 0, format SPICE: Can't locate resistor model (...)
Hi I am trying to simulate a spice netlist through a spice testbench in nanosim, but I keep getting the error highlighted in red below. The spice netlist was generated using Design Architect by Mentor graphics using tsmc018 technology. I call this netlist in the tesbench I created. The spice test bench is given to nanosim. *******************
Good day! I'm having my post layout simulation now. I'm using HSpice but it would took me weeks to finish it. I want to use nanosim. Please share it to me where can I have one.
Hi: I am trying to use nanosim to generate current sources (in fsdb format) to be used as input for EMIR simulation in a different tool. . In order to do this I am generating a probe file ( tap points) in nanosim format (report_branch_i < device_node> ) from a dspf file ( output of StarRC). However, the above format ( i
Hello everyone. Can anybody who is familiar with the Nanotime STA tool help me? here is the information after trace-path: Warning:Simulator Warning: Net DATA failed to switch.(DELC-004) Warning:Failed to get delay from pin xxx (net DATA) edge rising to pin xxx (net DATA) edge rising ,unable to trace further.(DELC-003) .
I extracted the parasitic data of layout using StarXtract. I got a SDF file. Now I want back-annotate the SDF file to original schemetic to do post-sim using nanosim. How to do it? Anybody could help me ,Thanks!
:-P Hello everyone here, I am a new one in this forum. I have a question about nanosim. When my simulation is almost about to finish, there shows an violation!!! 100% done segmentation violation signal-11 ... Nomatter how hard I try, it just shows up again!!! Can any one help me with it , Thanks a lot~ :-):-):-)
Hi Guys, I'm new in nanosim, and I'm confronting with the message: nanosim: ERROR: No supported SPICE models found and no technology file specified... Everything is correct: - my circuit (well synthesized) - gates in circuit are well specified - def. of transistors as well - supply + config - spec. top Does any-one has an idea, wha
how to include bitline metal layer capacitance in memory design using nanosim? It seems the total bitline cap is very small in my design, about 100fF for a bitline with 1024 memory cells connected in 130nm. I am wondering if the metal layer cap is included. Thanks for any suggestion.
I'm nanosim user. nanosim is release out of synopsys. When I read nanosim user guide, following comment is founded. The set_sim_eou command controls nanosim simulation engine accuracy (sim option) and nanosim MOS modeling accuracy (model option) during circuit simulation. An additional EOU option is (...)
SIMetrix, Multisim, Hspice, nanosim, LTspice are a few others, but they are mostly doing the same thing - SPICE. LTspice is slightly different because it is the only one that can use National Semiconductor's power supply models. SIMetrix has SIMPLIS which is for switched mode power supply design but I don't know much about it:
Anybody knows how to measure current of X1 as follows, it seems nanosim can only measure elements starting with M, C...and so on .SUBCKT INV1X1 A Q **INV Part X1 Q A VDD! VDD! PFET L=120E-9 W=560E-9 X2 Q A GND! GND! NFET L=120E-9 W=160E-9 .ends