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Ncverilog Simulation Time

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5 Threads found on edaboard.com: Ncverilog Simulation Time
I used to run ncverilog simulation with +nclibdirname+ABC option. ABC is compilied library for simulation, but it is very large. Every time I have to delete it manually. Is there any way to delete it automatically by ncsim? It seems ncsim has option -clean, but it seems only valid for INCA_libs.
I am getting hold time violations when simulating a design in NC-Verilog. The error message looks like this: Warning! Timing violation $setuphold( posedge CK &&& (flag == 1):120 NS, negedge D:120 NS, 1.000 : 1 NS, 0.500 : 500 PS ); File: ../synth/ibm18.v, line = 6410 Scope: testHarness.mcounter.\rstPip
i am trying to do a simulation with a pre-CTS sdf, so i am forced to hack the clock tree cell delay and interconnect delay to 0, but it will cause hold timing violation on DFF, so, how can i turn off "hold" timing check in ncverilog? i know, i can make sdf annotator ignore hold time annotation, but the verilog library still has that specify...
Hi, I am new to EDA tools. I have encountered the following problem. I have a netlist generated by XILINX. While simulating this netlist without SDF file I am getting the fillowing error: ncsim: *F,INTERR: INTERNAL ERROR Observed simulation time : 100 NS + 150615038 ----------------------------------------------------------------- T
Hi , Use ncverilog command line option , its a 3 step process (does compilation , elaboration & simulation) . +notimingchecks speeds up the simulation process , but at the cost timing violation checks which is really required in a gate level simulation. You can suppress the default generation of Log (...)