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Ncverilog Simulation Time

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5 Threads found on edaboard.com: Ncverilog Simulation Time
I used to run ncverilog simulation with +nclibdirname+ABC option. ABC is compilied library for simulation, but it is very large. Every time I have to delete it manually. Is there any way to delete it automatically by ncsim? It seems ncsim has option -clean, but it seems only valid for INCA_libs.
I am getting hold time violations when simulating a design in NC-Verilog. The error message looks like this: Warning! Timing violation $setuphold( posedge CK &&& (flag == 1):120 NS, negedge D:120 NS, 1.000 : 1 NS, 0.500 : 500 PS ); File: ../synth/ibm18.v, line = 6410 Scope: testHarness.mcounter.\rstPip
i am trying to do a simulation with a pre-CTS sdf, so i am forced to hack the clock tree cell delay and interconnect delay to 0, but it will cause hold timing violation on DFF, so, how can i turn off "hold" timing check in ncverilog? i know, i can make sdf annotator ignore hold time annotation, but the verilog library still has that specify...
Hi Ajeetha, Thanks for your suggestion. I tried running simulation with delay_mode_zero option with Cadence-ncverilog tool. This could not solve my problem. Can you suggest something else?? Thanks Mahesh I was suggesting delay_mode_unit, have you tried that? There is a detailed method of "divide and conquer" t
Thank you for reply. In fact, just as you said, we are now using formal check(lec)+STA. But gate simulation still needed in some cases. (rtl simulation has the same question) Here i just want to know is there some tips to speedup ncverilog. I've tried +notimingcheck -access,etc, it really works, but the anxious is TOO long (...)