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168 Threads found on edaboard.com: Ncverilog
Hi I am running simulation on ncveriolg through command prompt. Actually, I want that verilog code should use my library cells. The library are in the path "/home/sarfaraz.ahmed/techlib/FreePDK45/osu_soc/lib/source/signalstorm/files/gscl45nm.lib" how I include this library in our verilog code . The verilog code is written here : module n
Hello. When I simulate routed-netlist by ncverilog, sdf do not annotate 100%.. sdf was made by prime-time. I attached ncverilog.log below. >> Reading SDF file from location "../../../back_end/6_sta/func/sdf/LOGIC_TOP.wst.max.sdf" Compiled SDF file "LOGIC_TOP.wst.max.sdf.X" older than source SDF file "../../../back_end/6_sta/fu
Hi I'm a student. I have ncverilog. but I don't know how to lint a verliog code using it. Please give me the linux commands to Lint the code. hal file.v
Isn't the commands like.... ncverilog -access +rwc \ -f file.f \ -top name_of_top_module_tb \ -timescale 1ns/1ps \ ..........and so on! Btw, I used to use irun for everything as Cadence is supposed to integrated all into irun long ago. Below is an excerpt from a RTL simulation script meant t
Hi, I manage to run gate-level simulation of my post-routed netlist with ncverilog, and i can observe the increased delay of all cells and nets at simvision. My only question is about the sdf statistics that ncverilog reports, as I would excepted 100% annotation but it reports only 2.67% for paths and 2.58% for tchecks. About th
Hi. As I know ncverilog have 2 way to simulation. one is single step by using ncverilog. the other is 3 steps b using ncvlog-ncelab-ncsim I want to know the benefits of SNAPSHOT, and What is the concept of SNAPSHOT? If you are using Cadence tools, you should be theoretically having access to the user guide for that
Hi. I want to prove clocking statement in systemverilog by using simvision. I can't prove the inside clocking block(module tb). module top(); logic clk; initial begin clk =0; forever #5 clk= ~clk; end itf u_itf(.clk(clk)); dut u_dut(u_itf); tb_u_tb(u_itf); initial begin $shm_open("./sh
I would like to communicate c with verilog. I find the Verilog PLI can solve my problem. I read this website to learn But I still can't work even a printf function. I use ncverilog for verilog compiler. What I done is below. I can't have a successful compile for this. It says that it
Hi you can use "ncverilog" for simulation and to see waveform you can use "simvision". If you need any information please check cadence documents. thanks
I have some problem. once, look at this codes. Runit- #!/bin/csh -f ncverilog +access+w+r ₩ -f ff.list ₩ +define+LEVEL=$1 text.txt- (so many define value is defined in here) .... Blar~Blar~ ... .... `LEVEL xx.v- Blar blar $fopen text.txt $sscan
hi, I back annotated netlist with the sdf file which is generated by Primetime from spef file. But when I was running the post-simulation with ncverilog, I got the messages, ncelab: *W,SDFRDE: Read error for default code, skipping annotation of tst13.sdf.X. ncelab: *W,SDFRDE: Read error for default code, skipping annotati
I used to run ncverilog simulation with +nclibdirname+ABC option. ABC is compilied library for simulation, but it is very large. Every time I have to delete it manually. Is there any way to delete it automatically by ncsim? It seems ncsim has option -clean, but it seems only valid for INCA_libs.
Hi, As far as I know, there is no much difference between ncverilog and irun. ncverilog is old command and irun is new command and have some extra features has been added. Thanks Hi. I am curious about "Why do you use irun instead ncverilog?" I usually used ncverilog. I think this is very simple.and good. Somed
Hello everyone, Following is my verilog codes (with some xilinx primitive, can be totally ignored or commented ). When I try to use ncsim to compile it: ncvlog async_fifo_ack.v I got the following error about the generate part! ncvlog: *E,UMGENE (async_fifo_ack.v,66|8): An 'endgenerate' is expected . I am sure my code i
Hi. I have met a error like this. can not find binding for instance 'illeagal_ws::assert_never' in worklib.xxx:v. What should I do for solve this? I used run script like this. ncverilog +access+rwc +define+ASSERT_ON -f ff
Hi, Are there any knowing how to run mixed mode co-sim on ncverilog? The command I'm using for the ncverilog is as below. ncverilog -f -l ./log/design_top.log \ +loadpli1=./nc_loadpli1/debpli.so:debpli_boot \ +pulse_r/0 +pulse_e/0 +transport_path_delays \ +ncstatus \ +access+rw \ +loadvpi="libvpihsim".so:nsda_vpi_startu
Hi, I'm running a mixed mode design that is using verilog for digital and spice netlist for analog. The tool is using ncverilog. I'm wondering that I can't see any response from the analog design on the waveform that is in a fsdb file. Is is a problem on fsdb dump? Suppose, the dump systemtask $fsdbdump is the same as that using in digita
Dear Sir, I'm running a co-sim by using hsim & ncverilog. Analog circuit is written in spice netlist. And digital circuit is in verilog. After running, some error message found as below. Error: parameter "pwr" not found for instance xsdi_rx_top.xtenbit_sdi_rx_topall.xtenbit_sdi_rx_top.xrx_sdi.xrxpll_yx_sdi.xlcvco_sdi_rx.xi18 Err
hi, I'm working with Novas and ncverilog together to dump waveforms. It is strange that the log always shows this message: *** Registering Novas Verilog system tasks... ERROR: TF TFTHRE The user defined task or function $fsdbDumpfile has already been registered. ERROR: TF TFTHRE The use
Hello all, I want to know that How to simulate STIL patterns in ncverilog? I have to use only STIL vectors not the STILDPV. Patterns are generated by TMAX (Synopsys ATPG tool). Please help me to perform this simulation. Thanks & Regards, Maulin Sheth.