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Hi, I want to designt a fast ethernet line (1 Gigabit) My SOC (xilinx Zynq) has to be connected to a PHY then to magnetics and finally to a RJ45 connector SOC-------------PHY-----------Magnetics---------RJ45 |---distance 1---|---distance 2---|---distance 3---| I know that thumb rule talks about 25 mm of distance between each component
can we take Cdiff +C1||C2 as the effective lead to lead capacitance?near. Not C1||C2, it's a series circuit, Cdiff + C1*C2/(C1+C2). CANH pin then Cdiff+ Ci +C1 is the total capacitange.No, Ci and Cdiff values are representing the same physical capacitance. Cpin = Ci + C1
Some distros are much more helpful / forgiving than others. Ubuntu worked out pretty well for me, on a Dell which has a near-orphan GPU. Red Hat / CentOS, I could never get the display right on. Seems like the "easy" installs want to set you up with the desktop / GUI interface on boot. That's not going to work out well if you don't have (that
Can anyone explain about what is 'Phi' and 'Theta' angle in far field radiation sphere setup, 156743
Yes. Your noise margin (for a fully settled output) is the distance from rail voltage to threshold voltage. At rails come together (I*R applies to both vdd and vss) the distance must shrink. And that's just for the simple static case. Now consider a case where a gate at the worst "sagged" point of the core, tries to drive another gate that's we
Hi All, am appealing to anybody who has a similar environment to give me a few tips here :) The internet problem is weird, the system default is ffox 70 that runs fine standalone but none of the quartus menu's that would invoke it (help etc) work you just get no response. The same is true even if you set the browser path directly to ffox instead
I want to design an array multiplier using verilog and need to dump it into FPGA, out of stratix III, Artix 7, and kintex 7, which FPGA I need to select, so that computation time of the verilog code of array multiplier will be less.
Hi, i have designed the 3D spiral coil using HFSS and terminated it with 50 ohm impedance using single Lumped port. But the data table of Z(1,1) shows resistance value in terms of milliohms. What changes should be made to get correct values of resistance and inductance? How to obtain proper S11 at 10MHZ?
Hello everyone, I am preparing a two layer PCB where I need to put a circuit producing negative voltage for Op-amp. The recommended design of the IC (ADP5070) which I am using strictly says to separate power ground and analog ground separate. My question is how should I connect Analog ground and ground plane, should I put a 0ohm resistance to it?
Hi, Should I take say 10 samples in 10ms = 20 samples in 20ms If current for that channel is beyond the thresholds then SSR of that channel will be tripped in 3ms. A rather curious requirement. The measurement may take 10ms ... or 20ms --> a bit more than 3ms tolerance The SSR switching time maybe is 10ms or longer --
Hi expert, Info: The pulse signal is 12V to 0V (normally condition it's 12V and whenever there's pulse it'll be 0V for 50 milliseconds). I try to read a pulse based signal (which you can consider it V4 and V5 as per image in attachment) from external circuit into my microcontroller through NPN transistor (which act like a level shifter). For
In a Interleave active clamp flyback circuit input voltage is dc and output voltage is dc but it is nature of pulsating dc (full bridge rectifier pulsating dc type waveform)but in my actual hardware of flyback circuit output voltage is not like that as described above but it is something like triangular signal so pls help to solve above problem to
Hello, I'm designing a low pass chebyshev filter using stepped impedance. I'm using the book 'Microstrip Filters for RF/Microwave Applications' as a reference. I have difficulty understanding how low and high impedances are defined. The book uses Z0L = 93 ohms and Z0C = 24 ohms. I could not find an explanation for these values, I searched
Hi, As you know, its not difficult to design and build an offline SMPS LED driver that can run at 235W output, and also be dimmable down to 25W output. (eg, a Boost PFC followed by a 2 transistor forward converter). However, its far more challenging to make it able to pass mains harmonic emissions at 235W, and also at 25W. This is because th
solve this problem in DFE equalizer please: 156507
Hi Guys, I need to have a high rate data transfer of about 10Mbps on a twisted-pair wired line over a long distance of about 1500 meters. From my searches, I came to the conclusion that over the long haul, protocols like the RS485 did not meet my needs. I think I should use parts that do some sort of signal modulation and demodulation themse
Lateral electric field in a MOSFET is not constant, it has a sharp peak near the drain. But I doubt that such a deep microscopic characteristic, even if known, would be used in an empirical reliability/degradation model. The foundries normally provide degradation models, that are (or supposed to be) extracted form the reliability measurements.
Hello, as in title "Has anybody tried to run Keras or "Tensor flow" frameworks on FPGAs. I don't ask for runing trained ANN on FPGAs, but I rather asking about running neural networks in training phase. I hadn't eficient Nvidia GPU which is handle CUDA, so I cannot run KERAS on GPU, hence my question about running it on FPGAs. Maybe somebody
Hi All, I need to develop an circuit and antenna that will be placed on a person's body, and generate a constant electromagnetic field (for medical purposes). The definitions I received for this project is to generate a field from 10Hz to 700Hz, with field strength of 0.2 mTesla (that is 2 Gauss). I'm not an RF engineer and have very limit
Hello everyone, I am currently designing two low noise amplifiers (which will respectively operate at ~20GHz and ~38GHz) with the same foundry process (D007iH from OMMIC). The transistors come as discrete chips (roughly 400x400x100 um) without via holes, the aim is to use inductive degeneration and connect the source pads to ground thanks to two