Search Engine

Nec And Schematic

Add Question

Are you looking for?:
nec schematic , nec more , nec more , nec more
1000 Threads found on Nec And Schematic
Hello, my name is Hieu. I'm a process engineer of PCB manufacturing company. We have an issue about white residue on pad. When we doing solder mask and run developer. We check again see the white residue. Anybody have an opinions about this issue ? Picture below 156883 156884
There are quite different types of ferrite beads, e.g. beads on leads, surface mount beads, chip beads, wound beads, with different impedance and frequency range and current rating. You should narrow down the range you are talking about. Chip beads e.g. mostly have impedance maxima between 100 MHz and several GHz. Low MHz range would be (...)
Its a long time since I used an LM3914 but I think it's possible to lift the bottom of the divider chain above ground to set the minimum reading. The LEDs then display linear steps from bottom to top of the divider chain. The internal reference can be adjusted up to 12V but I think, and it isn't clear from the data sheet, the reference can be disco
Hello, I am trying to convert a real signed number into 2's complement in verilog for the sake of testing only. But I get "don't cares" when converting to binary. I am new to Verilog and not sure how to do it. My code is shown below: module tst(); parameter INPUT_PORT_WIDTH = 65; // Input filter data {1,64}
Hello, I am trying to do Power integrity analysis using PIPRO, Keysight ADS software. I have imported a layout in PIPRO setup. For PI_AC analysis, I want to assign a schematic as a component model to an IC (Packaged chip) for analysis. How can I create a component model of a schematic for use in PIPRO? I have tried creating a symbol but
Appears that both supplies have an externally asserted, hard turnoff (maybe the battery-drop, but maybe some other "feature" of the power supply controller(s). A question right off the top is, when you add the "large capacitor" does the discharge ramp look like dV/dt=Ioperating/Cbigfat, or is it getting jammed to ground by some external, much l
Hi, We are talking about HF. Thus this still is far away from being a GND plane. All the traces have the same length as before ... and for HF the width doesn´t play much a role. Simple method: Use double layer. Make the whole layer GND without any other traces/signals. Use short traces to connect each single GND line with a via to GND plane.
hello guys, i would be thankful if you help me to find how to calculate ib of this PNP ??156870
Please help me to find total,dynamic,leakage power dissipations in a simple inverter circuit using LT Spice XVII
156807 I need some help to design this circuit in ADS and reproduce the corresponding S parameter graph. FET model is NE3210S01. I have tried multiple times but not getting the result. VDD =0.4 V. I_DD=30 ma.
Hello! Please suggest how to generate pulse with 100-200us rise and fall time, 500-1500us duration. Voltage/current precision regulated 0-30V, 0-400A depending of load.
Hello! I tried to write my own code for 2 push buttons to rotary encoder (UP/DOWN Quadrature generator) I have flashed it (ofcourse with changed ports) on PIC16F648 and it works perfect, it also works perfect in Proteus simulation with PIC12C509 (C509 was the closest i have to F509). The problem comes when i program it on real PIC12F509 - the c
I'm trying tu simulate a resonant structure with fres = 2.87 GHz. The solution of my simulation yields the desired frequency, though when I look at the magnetic field distribution at a coil like structure, I see that the magnitude of the field is weakest in the middle, which can not be true! I tried to figure out what I might have done
hi, I want to understand I/Q modulation and demodulation process. I want to module a 10MHz bit stream (each bit has 100 nsec duration). Bit stream is in the form of 0 and 1. I want to perform BPSK. How can i convert it to i/q base-band? What is the significance of I/Q modulation and demodulation? Regards
Hi I have a 0-100uA analogue meter (needle) that has a marked scale of 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 and subdivisions between these. I want to be able to measure voltage of 0-10v with it, but the marked points to represent the actual voltages. In other words, the point 10 to represent 1v, the point 50 to represent 5v, the point 90 to r
Hi All, while hotplugging(5-8 times) FTDI chip usb-uart console onto my laptop; the processor reboots, this rebooting process is intermittent. the processors uart lines are connected to the consoles uart lines(I/O level 3v3 both processor and console); currently on the uart's TX and RX lines both, there is a series 100 ohm (...)
Hi, I want to design a differential Amplifer, and I want to start from gm*ro first. However, I can't determine the gm and ro in Cadence.
Hi, The following XC8 C Code just reads the ADC input?then if above a certain value, it then outputs a PWM out on a pin. Do you think this code is OK? it builds fine. The ADC had loads of registers and it didnt look like you had to bother setting all of them? It would be good if microchip had like an "LTspice simulator " for their microcon
Hi For an offline power supply for supplying a Class D bass guitar amplifier with peak power of 720W (obviously the average power is 1/8th of that), would you say that the transient response is very if the input rail to the class D amp sagged in voltage when a note was hit then that might make the bass sound a bit poor? ?and a
Hi, can anyone recommend an EVN or stacked FPGA system for capturing a still image? preferred 720p. I would like to trigger a snapshot - freeze the video and transfer the image via USB to a PC (via FTDI or Cypress USB chipset). The picture should only be transferred once the trigger occurred. This would be my first application with a camera

Last searching phrases:

and nor | and nor | and nor | keep out | throughout | and nor | and nor | and nor | and nor | first course