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44 Threads found on edaboard.com: Negative Cap
With respect to this a 12V supply I am only getting about -7V out of it with a CMOS 555. Does anyone have any suggestions on how I could get it closer to -12V?
Its very simple. The impedance of ideal capacitor goes to 0 when frequency is infinite (in lin-log scale it is a straight line with negative slope). When You connect resistor in series with cap, at frequencies for which capacitor impedance is lower than resistance You start to see a constant value of impedance equal to (...)
Hello I want to cancel the gate to source capacitance of one mosfet transistor in a circuit, I want a negative capacitance that put it parallel to gate-source, Is there any simple circuit just with mosfets that do this?
i have another question too, apart from polarity, i found this cap drop power supply design from ST too : 122552 which uses both positive and negative wave of input 220V, like the maxim design but ST uses less components. i saw ST design in a meter application note, not talking anymore about power supply output capacity ( li
Hello, I would like to build an ideal integrator in Cadence. Currently, I am using "VCVS" as an amplifier shown in the fig 117666 When I simulate the circuit, apparently, capacitor feedback does not work properly. The opamp model acts like a comparator. As long as negative input has a larger voltage output shows the mi
All relaxation oscillators work on charging up a cap with some hysteresis involved. To use a comparator , with hysteresis the cap charging must be from negative feedback R and hysteresis from positive feedback ratio Rin_equiv/Rf ~ % Hyst. ., but must be biased near Vcc/2 as in datasheet Fig 44
Try again >18kV min for trigger >0.62us .. choose a few us with cap 540V~1889V for reliable trigger With only 300Vdc on cap, trigger must be increased. Duration of lamp depends on size of capacitor & voltage , as lamp is a negative resistance avalanche with an positive power series ESR where Impedance parameter. (Ko) (...)
Hi, The attached image shows a pulsed transformer secondary. The transformer can output both positive and negative pulses. I have used a silicon diode to cut off the negative pulses. What I need is to cut off the negative pulses, but also regulate the positive pulses using a zenner. Can both jobs be done using a single zener and how (...)
The base-emitter voltage of each transistor becomes reverse-biased when the capacitor drives the base to a negative voltage. The reverse voltage is too high for the transistors (the maximum allowed reverse voltage is 6V) and causes the base-emitter to have avalanche breakdown. The supply voltage should be reduced to 7.5V or less to avoid it or diod
With the 10k fixed resistor, there are some clipping on the negative cycle and oscillations near the crossover that show up in my simulation. With that reduced to 2.2k and the 0. 22uF cap made smaller (22nF); I get 4.5W rms audio at less than 0.1% THD with a 1kHz test input. It seems to work well from 20Hz (THD 0.3%) to about 10kHz. At 10kHz, disto
You need to apply negative voltage right?
The capacitor in pin #6 is reversed, pin 6 is negative compared to the GND so the - of the cap goes to pin 6 and + to GND
In the ideal case a capacitance in parallel to a voltage source is charged immediately. In the context of that slide the charge deposited on the cap in parallel with Vin doesn't affect the rest of the circuit since the input voltage is still Vin no matter the cap. The capacitor at the negative input of the (...)
hi sorry, diode 4148 is used highspeed switching diode. Ok, why? What if we remove it, Q3 will not conduct in the negative part of the voice signal? thanks
Source/emitter/cathode followers all suffer from th same effect:- on positive going signals the device "switches on" and its output impedance is ~ i/gm || Rs/Re/Rk. On negative going signals, the device will try to switch off due to stray capacity holding the source positive while the gate goes negative, hence the output impedance will be (...)
nothing to do with SDC. Check the skew between those points. If its too high, inform to CTS engineer. If combo logic between Pre-CTS and Post-CTS is too high, check the reasons. Is fanout is more or cap is increased?. you see some negative slacks after CTS . Need analysis for this. If you can share the timing report, I can tell you the issues nee
"negative miller capacitance" aims at reducing the input capacitance.
During the positive half of the AC cycle current flows through diode to the load and charges the capacitor. During the negative half of the AC cycle no current flows through the diode, so all the current for the load must come from the cap, causing it to discharge. The smaller the cap, the more the voltage will drop (...)
It is expected that it will oscillate, as the cap will introduce a negative phase shift to the loop response. Besides, that is not the classical widlar bandgap. You need the circuit, just google for it.
i design a cap type charge sharing sar adc , it needs to be dischage when each conversion cycle. please see the pic show as below , the node vx=0 when sampling mode , and it is pull down by N3. but when the hode mode , the N3 should be disable. but , since the vx will be negative voltage , the MOS N3 body diode will flow to have a leakage