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I'm unable to recognize a charge pump topology. Presently you are just periodically shorting the power supply. Reconsider! An inverting charge pump would switch the positive terminal of the pumping capacitor between supply and ground. And the negative terminal between ground and output node. You may want to sketch a combination of (...)
It's a well expectable effect of MOSFET gate-drain capacitance Cgd. Rising Vgs edge will first transfer some charge to the drain node before the threshold voltage is exceeded and the drain is pulled low. Can't be avoided by a single ended FET stage. Possible solutions depend strongly on your application. You may want to feed a compensating ch
The left side is a half-bridge, one transistor is On while the other is Off. The capacitors charge to 1/2 supply voltage each. The node between them is 1/2 supply voltage. Operation might be described as single-ended class B. True AC (at 1/2 supply voltage) goes through the transformer primary. This allows a reduced step-down ratio. [url=o
I have read BSIM manual for charge partition in channel. However I don't understand one thing; when using 0/100 charge partition scheme while all of inversion charge is accounted by source node, how is capacitance measured (since Cdb = dQd/dVb). Thanks.
In the DC or transient analysis, you can calculate the charge at any node using the equation Q=CV where C is the node capacitance and V is the node voltage.
in a fully differential switch cap integrator the output common mode is set by a switch cap common mode feedback circuit. the theory of this can be applied in various ways. basically apply charge to a cap and switch the cap into your high impedance node. just remember a charged cap being applied to a high z node acts like a (...)
Hi, The question is related to Pspice modeling. I want to model a capacitor using the equation Q = C*V. The reason behind this implementation is, 1. I can access the voltage across this charge source. 2. I can model a capacitance which has the dependency on the voltage across it. In pspice reference manual, there is way to model a
There is a power supply circuit which we have built over 70,000 units in almost 9 years. And it has been working reliably for all that time, even during extreme environmental conditions. We would like to reuse this circuit for an almost identical application. We actually have built several dozen prototypes and they work just fine. But we would l
Hi, I am designing a hybrid content addressable memory (CAM) using cadence and I need to build a verilog-A block to switch modes. In the read mode, I need to pre-charge some nodes then make them floating. I tried different verilog-a lines but the code always fails. For example, I tried using the following line that I found while searching for a
Looking at your schematic... Running a simulation... One end of the secondary is connected to the node between IGBT's. It only conducts when either left-hand IGBT is switched on. This technique allows the capacitors to send juice to the transformer, in the reverse direction. Is this the method that lets you charge the battery? Looks clever. The
116569I designed charge pump like attached image. When UP signal is turn on (width 100ps) current of pink color node switching quite properly. but problem is that mirroring current of UP current(blue color node) is not fast switching. so how can i increase switching speed of bule color node current?? i want to in
I read the book from Maloberti, which says that: "A charge injection into a low-impedance node will only cause a glitch whose duration depends on the value of the node impedance. However, a charge injection into a high impedance or capacitive node causes an offset that can be problematic, especially when (...)
Is it possible to do the similar thing for InGaAs image sensor? I notice each InGaAs pixel is followed by a transimpedance amplifer. Can they do the CCD implementatation where they transfer charge from this pixel to next pixel? instead of using an amplifier for each pixel, for noise reduction reasons? and use floating diffusion as the output. Th
That's what you'd call self-cascoding, and it works well (better than a single long gate) in some cases, but can also have some issues relating to what the mid-node gets up to away from DC (charge pumping, RTN, etc.). But the usual reasons for fingering (interconnect current capacity, gate resistance) don't really apply to L.
Questions: * Your schematic has several stages. Did you try a single stage? Did it work? * Are your mosfets biased to a sufficient volt level so that they turn on? (It needs to be greater than the node at the source pin.) * Which capacitor accumulates the output voltage? The neighboring mosfet needs to be biased several volts higher.
Hi rajni, have you already made the SNM curve for hold?? if yes ,just apply the concept of read i.e. apply initial condition in both the lines by setting them high using .IC command format being .IC V(x)=XXv where x is node and xx is voltage to which you have to charge your bit lines and then set the word line high. While in Read connect the bit li
The tunneling node will be driven to high positive or negative voltage to drive charge into the floating gate. However this schematic looks like it's missing something - there is no explicit return path for the tunneling current. I have seen other schemes where there is another electrode on the tunneling FET.
I am trying to find the critical charge of a node by using current double exponential model I=Qt K (exp(-t/t1)-exp(-t/t2)). I am injecting a current which follows the above form. To find the critical charge I sweep the value 'Qt' until a change in the data is observed. Simulating D-Latch 1. when Qt=17fC there is no change in the (...)
97455 The circuit of charge pump is showed in the picture. What I am confused is that if there is not a unit gain opamp, voltage of node N1 and N2 would not change too much , so charge sharing is not terrible. But some papers realize charge pump with the unit gain opamp to reduce charge sharing. Why the (...)
Hello, please I have a question How is the output current (I=Gm*vin) from a folded cascode transconductance block taken to be introduced to the integrating switch " controlled by clock" to be integrated on the sampling capacitance of a charge sampling filter ? , from which node should the output be taken ? , the output current taken from the outp