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Hi I want to make a voltage selector circuit with opamps and diodes etc. (no IC's except opamps) but I couldn't find a way, do you have any advice for me ? Its like a dot display level meter (dot not bar) but I can not use LM3915 etc. I have a varying DC voltage and want to make a circuit that choose a specific path for its amplitude. I don't ne
Hi, I have a fsdb file. I am converting it to vcd with the fsdb2vcd command. I am opening the vcd file with the simvision tool and the tool converts it to .trn and .dsn However when I open the database I can only see the wave values. I cant access the source code or the schematics of the simvision tool (these options are usually (...)
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I don't even no where to begin with this one. I have designed an Arduino Mega based irrigation controller. The hardware is just a Mega, with a data logger shield, an ESP13 shield and a 8 x relay board. It has been working impeccably at 4 sites. But I have taken it to this one house and all hell breaks loose. Just seemingly random (...)
Dear friends, I am trying to design a floded cascode OTA for the sample and hold circuit that should work with sampling frequency of 5 MHz, this requires me to have an OTA with a typical GBW of 100 MHz. I am using 0.35 um CMOS technology with channel length I st for all the transistors to 1 um. The problem I am finding it very difficuilt to a
How ?mathematically? does adding a capacitor (series or shunt) change the electrical length of a coaxial resonator?
Hi I want to build a power meter for 1-30MHz) that can be able to measure down to -100dbm. I am thinking of using the mar8 in series with the ad8307. Is the preamplifier part ok (bias resistors and choke)? I put a preamp input 50R shunt to ensure good match at all frequencies, is what I have done ok?
Dear Friends, I finished with the design of single ended OTA. the GBW was achieved is 20 MHz by driving capacitive load of 10 PF. Now I chnaged the design to fully differential OTA and I kept exactly the same biasing current or circuit transistor ratios, then I connected the smae load of 10 PF differentially between the two outputs to make a com
Could anyone please explain the difference of Incident field>>scattered field>>total field>>incident field in HFSS Software. 156761
sometimes you want to know the resistance of a running circuit, some components have different resistance in off or on state, like MOSFETs or bjt, how can I accomplish it without ruining the circuit? it will be useful to calculate the dissipated energy of a continuous circuit and its efficiency though.
Hello guys, I have implemented a PFD and Charge Pump and I wanted to do a simulation for them as part of a PLL. without the need to perform verilogA components in cadence, I understood there is a way to take a complete PLL design in Simulink and replace some components with transistor level components from virtuoso. here is a link (...)
Hello guys I am Will from Levetop semiconductor. Our main product is LCD/TFT graphic controller, support resolustion: 320*240 (QVGA) 800*600 SVGA , to 1280 *1024 SXGA. Support 8/16-bits MCU parallel interfaces, and SPI, I2C serial interfaces Built-in Ggeometric Drawing Engine: provide Point Drawing, Line Drawing, Curve Dr
Are there software that allow you to simulate the charge distribution in the semiconductors? I general, are there software that allow to simulate behave of different combination of semiconductor?
Hello to all ! getting some info from AN1292 (Texas application for LM5642 ),I made dc-dc converter to use at a solar controller. At test with no load the converter not work . no output, no pulses 200khz to drive mosfets. it seems to be disable ( on/ss pins below 2volts ). I was checked hardware for errors many times , but I don't find something
Hello, I need to calculate the CANH to CANL capacitance in following circuit. 156753 In the datasheet of the device the CAN input differential capacitance (Cdiff) is given as 10pF and additionally CANH and CANL (Ci) input capacitance is given as 20pF. e.g
I made a helicail coil and have about 250 turns, how can i made it to be natural resonance?
Is it possible to reduce leakage current by applying Vgs=negative (NMOS transistor) instead of Vgs=0? I notice in my simulation that at negative Vgs the leakage current is lower and it is proportionally lower the more negative the Vgs. What is the relationship between leakage current & Vgs (negative)? Are there plot or formula I can look into fo
Could anyone advise about the verilator width warnings below ? verilator -Wall --lint-only in_buf_load.v %Warning-WIDTH: in_buf_load.v:35: Operator ADD expects 12 bits on the LHS, but LHS's VARREF 'idx_n' generates 9 bits. %Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Warning-W
Hi, I've searched through here and on google but haven't found anything about this. Typically, latchup is illustrated with nmos and pmos. The SCR is drawn based on those two devices. Is that to say that if the pmos was a p-diode or the nmos was replaced by an n-diode, there would be no latchup concerns? The question comes from some tests I've put
When AD7321BRUZ collects voltage, a spike voltage appears at the input every time it is acquired. After the input is opened, the ripple voltage is shown in the following figure: 156758 156759 Can you explain this situati