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1000 Threads found on edaboard.com: Noise Name
Hello, my name is Hieu. I'm a process engineer of PCB manufacturing company. We have an issue about white residue on pad. When we doing solder mask and run developer. We check again see the white residue. Anybody have an opinions about this issue ? Picture below 156883 156884
Hi, Gurus, This circuits is another company designed for MIC, then this MIC+/- links to my designed module. Then weird thing happens, the MIC volume is not stable with strong noise. Attachment is my audio circuits, please note in real there is a 604 ohms resistor between the left ends of C400 and C402. I am afraid that the other company's A1 &
Note the different resistor arrangement around the triac! The Chinese design uses a capacitor to filter noise from the gate and to partially snub spikes from across the line. For driving a heater which is mostly resistive, the capacitor isn't essential but I would guess it is marketed for switching reactive loads too. You really don't want a 330 Oh
Additionally the probe "loop area" (between tip+shaft, and ground clip) is an inductive pickup for all the inductor leakage field, and your choice of ground- point embeds more or less I*R, L*dI/dt voltage noise from circulating ground "plane" currents to what the 'scope channel sees. Output filter wants low ESL/ESR, but the inductor also contr
I agree that the datasheet is very clear about expectable output voltage. But if you plan to measure 500 ug acceleration, you should carefully read the datasheet info about noise density and temperature drift.
156744 Hi, For a typical double balanced Gilbert cell, how to match the RF input to 100 ohm? The zero frequency input impedance should be infinity. Even when frequency increases, the input impedance doesn't change significantly at sub-6GHz range. I understand that inductive degeneration can help with input-match
Hi all~ I'm trying to simulate the phase noise of my VCO and I used EM simulator to extract port to port s-parameters (all ports including IND and MOS,,...) and applied the results to cadence schematics through nport in analogLib. PSS/Pnoise results of phase noise in cadence was so bad and it shows difference of more than 10dBc/Hz (...)
I don't even no where to begin with this one. I have designed an Arduino Mega based irrigation controller. The hardware is just a Mega, with a data logger shield, an ESP13 shield and a 8 x relay board. It has been working impeccably at 4 sites. But I have taken it to this one house and all hell breaks loose. Just seemingly random and unrelated
First of all yes it is homework but I worked on it and stuck at only this part. Maybe I am approaching on wrong side I am open to every advice. I need to design a environmental noise checker circuit. I am not allowed to use any IC except OPAMPS! Passive elements (resistors, capacitors, inductors, diodes), LEDs, Analog Microphone, DC Power Supply
In ASIC design, is there any relation between IR drop and noise Margin ? and If yes, then how?
Hi, what does the warning mean? "Adaptive solution setup, process hf3d: Port 2, solving for derivative wrt 'variable name', for mode 1 out of 1 for H-field Adaptive solution setup, process hf3d: Port 2, solving for derivative wrt 'variable name', for mode 1 out of 1 for E-field"
is the diode/cap the right way round on the sec side - i.e. Tx phasing ... ? - - - Updated - - - also try a 22 ohm gate resistor - for starters - reduces the noise ... - - - Updated - - - also 150pF on pin 7 to gnd... - - - Update
I have a prototype board which has two RF modules on it, a 2.4GHz Wifi module (ESP-01) and a low cost 433.92MHz RF receiver module (Wenshing RWS-371F-6). My 433MHz transmitter (a remote control) sends data encoded in manchester to be decoded by the receiver, this part is working well. The data rate is 2000 bits per second and I am using 433.92MHz S
Hi, What technical informations did you give that we can use to find a solution? When a monitor flickers, then usually it's because * monitor type: input signal range * graphics card output signal: resolution, frame rate, (Maybe even a mature "interlaced" signal is output by the graphics card) * noise introduced into the monitor cable (signals):
When I simulate a switched capacitor circuit for with PSS, PAC and Pnoise, the Pnoise does not come out right. I was expecting the output noise to be 4KT(1/(f*C)) just like it would be a for a continuous time RC filter. Rswitch = 0.01 + 10 Ohm (noise generation is enabled for each resistor) Fsw = 1MHz Cfly = 1pF (...)
In fact there is no "CMOS transistor" - there are NMOS and PMOS. As a rule "RF guys" appear to prefer the zero-VT device for gm and IDsat, relative to capacitances. You can find canned NMOSFETs for lower frequency applications. Anything over maybe 1GHz probably wants integrated transistors. Kind of wasteful for a 1-transistor LNA (study p
Hi, i designed a sinusoidal pwm amplifier (3KHz to 20KHz) that regulates its output voltage reading the RMS value of output current. The RMS is obtained squaring the signal sampled by AD converter @200KHz and then applyng a FIR filter with 120 TAPS. The advantage of this method is that the settling time of the FIR (so the response to amplitude c
Hello, I want to do behavioral simulations using SystemVerilog as opposed to using Verilog-A and Verilog-AMS for Mixed Signal Designs in Cadence Virtuoso/AMS/Incisive/Spectre. How can I use SystemVerilog files ? Can I use them just as I use Verilog-A or Verilog-AMS files ? Will Cadence Virtuoso/Spectre/Incisive/AMS recognize SystemVerilog a
The code should work, but measuring peak-to-peak current magnitude is sensitive to waveform distortions and noise and in so far the least accurate way to measure AC current.
Hi , i'm trying to find a low power solution to switch +/-5v on/off with daisy chained SPI to switch on/off TI PGA2500 preamp prototypes i'm designing. I already have SPI running to the PGA2500 IC's for other control ( phantom power switch using optomos ) The optomos switch phantom from GPO pin controlled by SPI in the PGA's but GPO pins no