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96 Threads found on edaboard.com: Noise Nmos
Why must the drive strength of the nmos transistor be much greater than the driver strength of the access transistors for better noise margin? How does the SRAM value become harder to flip if the drive strength of the nmos transistor is higher?
If you are after minimum supply induced noise in a (say) RF amplifier, you might connect the deep NWell to substrate potential, and the PWell's guardring or tap as well. This will give multiple layers of Vss-referred capacitance with no real supply coupling path. If you tie DNW to VDD and PWell to VSS then you have a large-ish coupling cap to the
I have a 2nd stage OP which use nmos input pair. Where should I connect the nmos body, ground or source? Which one has the better noise performance?
I have a 2nd stage OPAMP which has nmos input pair. Where should I connect the body of nmos input pair, ground or source node? Which one has better noise performance?
That circuit cartoon provides no common-mode authority for the inputs. Where are they sitting "naturally" and is that within the proper-function common mode range spec? If this is a single supply comparator, does it work with both inputs near ground (neg supply)? An nmos-input design would not, the input pair would be choked off. It appears that
Isolated devices are the devices which have their substrates isolated from the rest of the circuit. This comes in handy usually when you need to use S-B connection in nmos devices, but if you use this as a design methodology you can significantly reduce the substrate noise coupling from whatever digital circuit you have on the outside. Some process
hello evryone.... does the direction of noise current source differ for nmos and pmos ???
Hi everyone, Recently I am using TSMC .18 mixed-signal technology to do some design. I am about to use a deep nwell to put all my digital circuit into it to get a good noise isolation. However when I run LVS I found all the nmos of those digital standard cells are recognized as the dnw nmos. I know I can use dnw nmos in (...)
This results in less output voltage swing and less noise margins.
Hi, I am designing a VCO, but confused with single-ended and pseudo-differential RO. What are the main difference between them, with respect to phase noise, PSRR, common mode rejection, et al. As I know, single-ended RO is less power consuming, better phase noise performance(because PMOS and nmos can be turned off ??), but its PSRR (...)
Hi, I want to simulate nmos and PMOS noise behavior in 130nm technology with Mentor Graphics tool, parameters as below: Vds=0.7V Id=185uA W/L=100/0.4 um in order to get Id=185uA, Vgs has to be set around 0.36V. I put a AC voltage signal with offset 0.36V, magnitude default is 20mV. The problem is, when I simulate AC noise (...)
I'm trying to simulate the noise psd of nmos. but when i performed the noise analysis and plotted the resulting output noise, it is zero over all the frequency range? could someone help me? thanks. 100961100962100963
I have a simple differential pair in hspice. I want to perform corner case and noise analysis. what shoul I do? in below you can see netlist: VCC 11 0 DC 5 VDD 12 0 DC -5 vb 4 0 1 M1 3 1 5 5 nmos1 w=20u l=.5u M2 3 7 5 5 nmos1 w=20u l=.5u M3 11 4 3 3 nmos1 w=5u l=.1u R1 5 12 7k .MODEL (...)
It depends on your offset and noise requirement. The pmos loading pair mismatch and noise will be reduced by gmL/gmI. gmL is gm of loading PMOS. gmI is gm of input nmos.
Hello Guys, Considering the LC-TANK nmos shown in the attached figure. What is the difference on the phase noise if the outputs are taken single-ended or differential? Besides the amplitude that will be folded if the outputs are taken differential. I?ve verified the phase noise performance, and they are equal in both cases: (a) (...)
The primary consideration for the type of input stage to choose is the icmr. Area, noise and offset are some other secondary considerations.
Hi AdvaRes, I need to know if the circuit posted by you have good noise margins as with 8 transistors? BR// Abhishek
Hi I am designing and simulating low noise amplifier using ADS software i need to enter W/L for the nmos IN THE CIRCUIT. can anybody help.
This is a full swing cross-coupled nmos latch. You can learn more about it from this paper: "AN OVERVIEW OF LOW-VOLTAGE VCO DELAY CELLS AND A WORST-CASE ANALYSIS OF SUPPLY noise SENSITIVITY" Mohamad El-Hage and Fei Yuan
can anybody tell me difference between single ended cmos ring and differential CMOS ring oscillator?? what is the role of nmos and pmos tail transistor i n current starved ring oscillator?? which one is better between the two? and which one gives better phase noise peformance?