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Noise Pmos Pair

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9 Threads found on Noise Pmos Pair
It depends on your offset and noise requirement. The pmos loading pair mismatch and noise will be reduced by gmL/gmI. gmL is gm of loading pmos. gmI is gm of input NMOS.
One reason is that pmosFETs have lower flicker noise.
I guess you are asking about the input pair of the differntial amplifier: 1) For lower noise, it is preferred to use pmos i/p stage 2)Based on the input common mode range ,i,e whether the input is towards the rails or the ground we need to chose pmos or NMOS respectively. 3)Some times the channel length modulation (...)
Agree with yxo. It is empiric rule. But pmos for diff-input-pair still has its merit such as no body-effect, low 1/f noise.
NMOS will be better in terms of gm and hence thermal noise and bandwidth ( bandwidth will be larger at the cost of a worse phase margin ). pmos will be better in terms of flicker noise ( however this might not be true depending on ur technology )
How about a pmos input pair, which requires lower input common mode voltage and has a better noise performance than an NMOS input pair.
and BTW, you can also use the pmos differential pair to reduce the 1/f noise.
i read that flicker noise in pmos is lower than hat in Nmos due to the burried channel, can anyone explain what is the burried channel?
Recently I designed a 3.3 to 1.8V 0.18um CMOS voltage regulator for one of my company's high speed (>2Gbps) project I realized that the output voltage of the regulater fluctuated a lot due the switching noise in the circuit being decoupled back into the regulator itself. I am trying to design the regulator hopefully without the need of exter