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# Non Positive

46 Threads found on edaboard.com: Non Positive

## Displaying floating point numbers in seven segment display

Hi, I doubt you have a floating point ADC.... Therfore I assume you get binary from ADC, and then generate floats in your software. I usually try to avoid floating point in a microcontroller. **** What is your display value range: * positive only? * largest positive value? * smallest positive non zero value? * Do you (...)

## Isolated Thermocouple Amplifier

What is the expression for Vo??? Voltage created by the thermocouple is fed to the non-inverting input. (I cannot tell whether it is positive or negative, therefore I'm not sure whether the output is positive or negative.) It appears that the op amp is set for a gain of 100. Rg adjusts the output voltage up/d

## Some common Analog terms

1)Why db ranging mostly from 0 to negative? peak at 0 level and as it decreases it goes negative? why no positive? 2)noise floor in -155dBm/Hz what's dBm? why its over frequency? 3)why resisitity express in ohm-cm? why cm which is length? not not ohm-area? 4)what 's a epi versus non epi wafer?

## Level shifting in OPAMP and HE100T01 interfacing problem

The circuit does in fact a negative instead of the intended positive level shifting. Quite obviously, a single supply non-inverting amplifier can't process the negative input voltages corresponding to negative currents. A simple way to achieve a positive level shift is to use two resistors and a reference voltage. No OP needed.

## How to configure op amp to produce a 0 to neg 10V swing from a 1Vpp pos signal

It might be possible if you can use a RRIO opamp in place of the 358. I won't draw a picture (no graphic sw on this computer), so bear with me. positive supply line to ground. Negative supply line to -12V. non-inverting input to ground. Signal to inverting input through a 1k resistor. A 10k resistor from output to inverting input. What happens is

## Operational amplifier

What is a "difference" opamp? Do you mean an opamp circuit with a differential input? Next time please post a schematic of what you are talking about. Here is an opamp circuit with a differential input. It uses a positive and negative power supply so its input "bias" voltage is 0V. If the non-inverting voltage is positive then the output (...)

## Positive and negative supply

I need to power a op amp. An opamp does not need a dual polarity supply if it only has an AC (audio?) output signal. You simply bias its very low input current non-inverting input at half the supply voltage with two fairly high value (100k) resistors and a filter capacitor. Then its input, output and feedback ground r

## Why this circuit oscilates?

Common base amplifiers are non-inverting and this one uses a capacitance divider feedback to the emitter for positive feedback at LC tank resonance with 0 deg phase shift. Thus oscillation is sustained when the loop has gain at resonance by ratio of Collector to emitter impedance at resonance. The Bias resistors control the dc current operati

## negative miller capacitance in OTA

All transistors have Miller capacitance which is from the inverting output to the input. In a differential amp , by adding caps by cross over ( From + out to + in and -out to -in ) from internal differential outputs, it tends to cancel the negative feedback with a lesser positive feedback with non inverting current or negative Miller Effect . Whe

## Rail to rail op-amp versus simple op-amp

There are different types of rail-to-rail opamps: some are only R-R on the output, some are R-R on both input and output. Many non-R-R opamps can go all the way to ground on the input, but not to the positive rail. You need to look at the specific op-amp to determine what it can do; they're all different. Some will just saturate if the input goe

## How to prohibit negative pulses out of the transformer secondary?

Assuming a transformer secondary outputs only positive pulses and negative pulses, a single diode can be used across the secondary, so that only positive pulses are out. Is there any other non-semiconductor way to do it by using a second transformer or a special winding etc?

## Op-Amp Positive Supply drops down..........

My personal preference is wiring each unused FET OP as unity gain buffer with non-inverting input connected to circuit ground.

## Help to tidy up Mono Synth Front end

... keep the same stage gain. I did try to use a non inverting op amp stage after it instead of two inverting stages but couldn't seem top get it to work correctly. After the tap of your poti you could do it with one opAmp and 4 equal resistors (say: 100 kΩ) , and a positive reference voltage of 7.

## An Op-Amp to amplify 1mV 40KHz signal upto almost 3.3V-5V

It's possible your zero offset has to be raised a bit, so that it will then detect a weak incoming signal. Although a single op amp has terminals built-in so we can adjust the zero offset, the quad 324 does not. So we must try a workaround. It ought to help if you were to apply a slight positive bias at the non-inverting input. That is what

The premise that V(inverting)=V(non-inverting) doesn't apply here. The positive feedback messes that all up. Look at it this way: The output is at VCC. Then the voltage at the non-inverting input is VCC(r1/(r1+rfb); call this V(ni). This means that the voltage at the inverting input must be greater than V(n1) in order to get the output (...)

## Warning: NON UNATE PATH IN CLOCK DOMAIN..

Hei unateness is an attribute, for ex: when u give any input to an inverter its output will be inverted. It is said to having an negative unate. Similarly a buffer will rise when input is high and falls when changed to low. so it is called as positive unateness. whereas as dftrtl rightly pointed in a gate like xor if a value goes to 1, depending on

## Phase diagram of s11 positive and always >0 deg

Can you post an S11 plot (on a Smith Chart with some frequency markers)? phase of S11 always >0 means that your antenna appears to be (somewhat) inductive over the simulated frequency range. This can be a combination of certain transmission line length and non-optimum match.

## non causal and anticausal systems

what is the difference between non causal and anticausal system.how could we differentiate both system with laplace transform

## How to simulate Hysteresis of a latched comparator [hlp]

if you dont have model of those chips use the specs and design the variables and tolerances if resistor positive feedback on any 2 stage invertor or 1 non-invertor chip

## simpe constant U/I supply. Would they work?

1st schematic should be emitter follower out, non inverting with negative feedback, and pull down resistor. but Q1 may overheat if Vin = 80V @ 100mA 2nd schematic may be overkill and also has positive feedback (NG) I suggest you use LM317 with transistor to use ADJ-OUT 1.250V internal reg drop for constant current control. See chip App notes.