Search Engine www.edaboard.com

Nor Not

Add Question

246 Threads found on edaboard.com: Nor Not
IC5141 is still not be installed under ubuntu7.04 , the glib file is nor correct. How to deal with it? Thanks.
I am facing a problem while using Design Architect(DA) on Solaris 10. I do not have any problem neither on Suse nor on Debian with DA. However with Solaris in DA I cannot see the system toolbar correctly. Instead a black box has been put. Backing store enabled by the way. I am attaching the picture . Thanks for any assistance
Hi as I see in the schematic M8 and M6 generate current of M30 nor vice versa. in quaesent, VGS2+VGS4=VGS8+VGS6 but size of M6 and M8 are 10 times of M2 and M4. so, Vt2 is not equal to Vt6 and Vt4 is not equal to Vt8 and from schematic, Vds2 is not equal to Vds6 and Vds4 is not equal to Vds8 (...)
i dont know influence of second nor input over the first one , but if it is not interfering , for cmos logic , output voltage should half of power supply and logic ic should work in linear mode if button pressed for time more than multiple of R*C value .
hello, everyone. I designing a layout based on 0.18u, the PP tool is SOC encounter. when i open the GDS file with virtuoso, I don't see the ACTIVE, NWELL, NSD and PSD. would you tell me is it correct ? thank you !
Here's some thoughts: 1) You need to look for worst case transitions. In a nor gate, to switch low, worst case is only ONE nmos device pulling low (not two), hence one signal should stay low (while the other rises). If you keep B low, the output sees parasitic capacitance from BOTH pmos devices, hence is the worst case transition. 2) Your t
CMOS NAND is better than nor as size of all transistors is equal for 2-input NAND. Size of PMOS is bigger than size of NMOS for nor. So NAND layout area is smaller.
not, NAND and nor are the base of modern digital design. The reasons are: 1. NAND and nor have smaller area than AND and OR 2. NAND and nor are faster working 3. All of more dificult devices are built from theese elements. Look for any trigger.
Signal Integrity Comparisons Between STRATIX II AND VERTWEX-4 FPGAS.pdf Do you have the same comparison generated by a neutral user (not Xilinx, nor Altera) ? Or the same information written by Xilinx ? thx,
hi guys, I have to assemble a nor flash,RAM and some sensitive devices on to a board. What are the precuations to be taken.like any electrostatic gloves,watches etc etc.. anyone out ther experienced in these areas..??????
Anyone could tell what's the benefits to use this software? As far as I know, none. Two of the main shortcomings are: 1) It is not of conformal type. It utilizes a staircase mesh. 2) It doesn't stop the the time domain simulation through checking the existing energy inside the simulated structure, nor does it use
nwo4life, It's best to tie inputs to a state that will force the output to a known state. This way, the outputs can not bang up and down in response to noise on the open inputs, creating noise and emi. . For example, tie at least one input of an And or Nand gate to ground ("0"). Tie at least one input of an Or or nor to "1". Tie clock inputs
1- Recently, What is the technology to produce a memory? I read an article about memory advancement but I do not understand it completely. It talks about nor-gate and NAND-gate based technology but I dont know about this technology. Can some one here show me the answer as clear as possible because I'm not an electronic enginer! Thank (...)
Neither - nor You can specify on the NEXT level what you want. If if does not lead to an efficient implementation it will not work. At least, if you oversee some critical effect because you have a unexperienced team, after silicon out. So get familiar what work at bottom, or the NEXT lower level, unless you start at the NEXT higher lev
Hello everyone, I am encountering an unexpected problem with my data analysis. I have to analyse an acoustic signal which has a large amount of peaks. The amplitude of the peaks is not fixed nor the time of each peak. What I want to do is to measure 1) The time interval between two peaks. 2) The time interval that a peak lasts. I (...)
CMOS NAND is faster than CMOS nor. not really sure about BJTs
Sathish, not gates (inverters) are routinely used in discrete logic design. Often the use of Nand or nor gates precludes the need. Regards, Kral
Be carefull... 6 bit MSB should have 12 bit accuracy not 6 bits. Neither resistor (~8 bits) nor capacitor (~ 10 bits) will give you 12 bit accuracy if you do not employ circuit techniques (like calibration, trimming ).
non inverting gates are built using inverting gates inverting gates are the universal gates like nand nor and not when u convert an inverting gate to non inverting gate an exta gate comes which introduces the delay
A PI controller is not a RTOS, nor does it require a RTOS. A PI controller is an algorithm that runs at periodic intervals, but this could be implemented with a simple timer or even a delay loop, with no RTOS present. An RTOS can execute a PI controller algorithm as one or multiple threads if an RTOS is available on the target controller.