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HI, i need some help on this simulation. can someone tell me how fix de error "Timestep too small", or review my schematic. tks
Hello everybody, I have a problem when use VCS from Sysnopsys. When I compile a verilog file: vcs -R -debug_all mndf.v +v2k -full64 But I can not run ./simv. I tried and error as below: --- Stack trace follows: Dumping VCS Annotated Stack: #0 0x000015554e279f16 in waitpid () from /lib64/libc.so.6 #1 0x000015554e1f5757 in do_
Here is what appears to be some sort of a folded cascode amplifier, but does not really match with any classic text book example. Does it make sense to you guys? 156931
I, personally, would design for worst case values. If you design for typical values, you're just asking for trouble. normally yes. treez is however designing logic gate delay. It should start with typical values, considering the full min to max range.
On page 125 of Power supply cookbook by Marty Brown (2nd Ed), Brown designs a pulse transformer gate drive for an offline half bridge converter. Brown states that the gate drive transformer would have the same voltage stresses as the main half bridge transformer?surely this is not correct? (the drive transformer is driving primary hi side fet fr
But am I correct in saying that differential mode coupled inductors have little theoretical benefit in cases when differential mode currents dominate? You don't get a smaller core by 'ignoring' tiny common mode currents. So the choice of individual chokes or coupled differential-mode choke is a practical one? Yes. I'm not even aware
Hi I need help to understand speed of SPI Ic MCP3004 Features: 10-bit resolution Four single-ended channels SPI interface ?1 LSB DNL ?1 LSB INL 200 ksps sample rate at 5V I do not understand meaning of 200 ksps sample rate at 5V. does it means mcp3004 can send one bit to slave at speed of 200 ksps ? Each bit take minimum 200 ksbs for
Hello everyone. I have an electrically very large polygon and innevitably the generated mesh is very large wich leads to impractical large simulation time. What i did was to seperate the polygon in 3 rings so i created first an outter ring and defined a local fine mesh(lamda/10) then i created the second ring and defined a more coarse mesh(lamda/6)
Hi!... Will anyone have a copy of the old programs used by picstart 16B? I'm in Venezuela and around here somepeople still use that equipment...
Please let me know that I have UV flame detector HF-24.His datasheet shows two voltages ONE is Rated Voltage (24VDC) and SECOND is Working Voltage (15 ~ 30)VDC. What is the difference between Rated Voltage and Working Voltage and maximum switching current (250mA)? I want to know what is the output of UV detector,is there VOLTAGE or CURRENT?
Hi, The attached is a picture of the inductor current in a synchronous two transistor forward converter just after going from full load to no load. (its an LTspice sim) As you can see the inductor current suddenly reverses to a badly high level due to the fact that the LT1681 has ?malfunctioned??.the LT1681 holds the ?catch? synchronous rect
As B-H curves in CST EM STUDIO are not containing the hysteresis loop(look below), Does it consider the hysteresis loop? if not how can I influence it? 156918 thanks;
need help with metal detector circuit if i use arduino/PIC micro controller ADC channel. 156811 if i want to switch the coil inductor at high current using mosfet for greater depth. because direct connection of switching signal from arduino pin is not the correct way for switching at high input current. and to use ADC c
Please help me to find total,dynamic,leakage power dissipations in a simple inverter circuit using LT Spice XVII
Hey guys! I've just started with electronics and I made this PCB for an amplifier which contains 2 transformers. Here's the layout (with some SMD components): 156871 The transformers are on the opposite side. This is my 2nd PCB and since this is an amplifier I wonder how the transformers affect the circuit (if it doe
Hello, I am trying to convert a real signed number into 2's complement in verilog for the sake of testing only. But I get "don't cares" when converting to binary. I am new to Verilog and not sure how to do it. My code is shown below: module tst(); parameter INPUT_PORT_WIDTH = 65; // Input filter data {1,64}
Hi, Page 122 of ?power supply cookbook? (2nd Ed) by Marty Brown details the design of a 280W offline Half Bridge Converter in Current mode with slope compensation. Current Mode is in theory not advised for Half Bridge converters due to potential imbalance of the rail splitting input capacitors. However, can we actually say that as long as
Hello, my name is Hieu. I'm a process engineer of PCB manufacturing company. We have an issue about white residue on pad. When we doing solder mask and run developer. We check again see the white residue. Anybody have an opinions about this issue ? Picture below 156883 156884
I am trying to study the effect of frequency changes in the first coil on the induced voltage on the second coil while a piece of metal is between them. The B-H curve of materials in CST library are not containing the hysteresis loop. Does CST EM STUDIO consider the hysteresis loop? if not how can I influence it? 156887[/ATTA
Dear All, I'm planning on using a transistor to drive a 75 Ohm coaxial line (RG6) with just a digital signal. From collector to VDD there will be a 75 Ohm resistor. The signal at the collector is than AC-coupled onto a RG6 coaxial cable. At the end of the long cable (100m, neglect the attenuation for now) there is a 75 Ohm termination. So if